• Post silicon power on leader of GNR. Responsible for bringing up HVM reset sequence, and inter-die DFX fabrics, pattern reuse between sort and class tester.• Tech leader of architect and logic implementation for DFX subsystem for GNR die. Responsible for fuse subsystem implementation, security fabric, DFD fabric, JTAG network and bridges, high speed SSN fabric, and cross die DFX fabric, and DFT logic time closure.• Tech leader of power management IP DFX subsystem development, a key IP… Show more • Post silicon power on leader of GNR. Responsible for bringing up HVM reset sequence, and inter-die DFX fabrics, pattern reuse between sort and class tester.• Tech leader of architect and logic implementation for DFX subsystem for GNR die. Responsible for fuse subsystem implementation, security fabric, DFD fabric, JTAG network and bridges, high speed SSN fabric, and cross die DFX fabric, and DFT logic time closure.• Tech leader of power management IP DFX subsystem development, a key IP for intel product. Responsible for security management, MBIST, Scan, and JTAG logic implementation and verification. • Post silicon power on leader of CDF. Responsible for HVM reset sequence debug, MBIST pattern debug, and ATPG coverage debug on tester.• Tech leader of architect and logic implementation for DFT subsystem for CDF die. It included JTAG network, high speed scan interface and network, and DFT logic time closure. Leader of implementation/verification of MBIST, BSCAN, and HVM reset sequence. and ATPG coverage. Show less

• Responsible for architecting and logic implementation of JTAG system for microprocess. A JTAG subsystem includes 205 TAPs and TAP network. It supports DFD features, security, power gating, PLL, MBIST, fuse, and sideband fabric. • Developed a tool flow to extract the JTAG system from RTL to verification spec, furthermore it automatically generated TAP validation test cases.• Responsible for verification of DNV JTAG system and its interaction to debug system, power gating, PLL, and… Show more • Responsible for architecting and logic implementation of JTAG system for microprocess. A JTAG subsystem includes 205 TAPs and TAP network. It supports DFD features, security, power gating, PLL, MBIST, fuse, and sideband fabric. • Developed a tool flow to extract the JTAG system from RTL to verification spec, furthermore it automatically generated TAP validation test cases.• Responsible for verification of DNV JTAG system and its interaction to debug system, power gating, PLL, and sideband fabric.• Leading efforts for physical implementation of fuse system. Includes analog design, digital design, on die voltage regulator, multiple clock domains, multiple power domain, analog circuit simulation, power grid simulation, and timing closure for digital logic• Responsible for architecting and logic implementation of microprocessor core DFX infrastructure. The DFX infrastructure included core scan ring structure, TAP, and SCANOUT• Responsible for architecting ScanDRC tool flow and ScanDrc rules definition for enforce scan, SCANOUT, and clock methodology of a microprocessor. The tool has been extensively used for many other projects in Intel. It significant improved ATPG coverage and ensured high ATPG pattern quality.• Technical leader of physical implementation and timing closure for DFX components in microprocessor core Defined and developed DFX methodology for Design. Show less

• Responsible and developed custom reset ROM automation design flow from RTL to layout in Tukwila. • Responsible and developed a tool flow to check scan clock slope and skew for Tukwila. Responsible for DFX methodology for design and test clock distribution methodology

• Responsible silicon validation and debug. Primarily involved in electrical debug for top level units and clock related verification. Developed a tool flow to quickly located speed failure on silicon with ODCS manipulation.• Responsible for developing DFX hardware infrastructure for Montecito microprocessor. Included Scan architecture, sample on fly, and clock DFX architecture. Developed DFX design methodology and guidelines for Montecito microprocessor• Responsible for DFX hardware… Show more • Responsible silicon validation and debug. Primarily involved in electrical debug for top level units and clock related verification. Developed a tool flow to quickly located speed failure on silicon with ODCS manipulation.• Responsible for developing DFX hardware infrastructure for Montecito microprocessor. Included Scan architecture, sample on fly, and clock DFX architecture. Developed DFX design methodology and guidelines for Montecito microprocessor• Responsible for DFX hardware implementation for Montecito microprocessor. As a DFX leader, support and help teams to understand Montecito DFX infrastructure for post silicon debug.• Custom design data path block. Memory Array design, dynamic circuit design, critical circuit and timing analysis with spice, static timing analysis, and circuit robustness analysis.• Responsible for clock unit logic verification, static timing analysis, and robustness analysis. Involved of PLL designs and clock distributions. Show less