Mark Espinosa Email & Phone Number
@ngc.com
11 phones found area 714, 909, and 703
LinkedIn matched
Who is Mark Espinosa? Overview
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Mark Espinosa is listed as Senior FPGA Firmware Engineer at Raytheon Intelligence & Space, based in Mckinney, Texas, United States. AeroLeads shows a work email signal at ngc.com, phone signal with area code 714, 909, 703, and a matched LinkedIn profile for Mark Espinosa.
Mark Espinosa previously worked as Systems Engineer III at Northrop Grumman and Systems Engineer II at Northrop Grumman. Mark Espinosa holds Masters In Electrical Engineering, Robotics And Computer Engineering from California State Polytechnic University-Pomona.
Email format at Raytheon Intelligence & Space
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AeroLeads found 1 current-domain work email signal for Mark Espinosa. Compare company email patterns before reaching out.
About Mark Espinosa
FPGA Firmware Engineer with excellent independent professional judgment. Can successfully perform professional engineering assignments while applying engineering principles, theories, and concepts. Currently has experience in Research and Development (R&D) and Systems Engineering teams and is able to innovate conceptual designs and perform analysis for both Mechanical and Electrical Systems. Is able to work efficiently in a team or independently. Specialties: FPGA Development | RTL Design and simulation | Hardware Integration and Testing | Analysis and Testing | ESD and Cleanroom Hardware environments | Meeting Critical Deadlines | Team Leadership and Collaboration | Client Relations & Presentation |Core: Xilinx Vivado and ISE, VHDL, Verilog, Mentor Graphics Questasim and Modelsim, Python scripting, C++, Matlab, Simulink, Synopsis SynolifyOther: Fusion 360, Simplify3D, Mathcad, Labview, AutoCAD, Solidworks, Pro-E, Machine Shop, Labview, Pro-Engineer, PSPICE
Listed skills include Mechatronics, Solidworks, Pro/Engineer, Labview, and 46 others.
Mark Espinosa's current company
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Mark Espinosa work experience
A career timeline built from the work history available for this profile.
Senior Fpga Firmware Engineer
Current- Successfully performed Ethernet integration & testing on Xilinx Artix7 AC701 and Virtex UltraScale+ VCU118 evaluation boards. Integration activities employed the used of Vivado Logic Analyzer, Wireshark, Python.
- Integration allowed for the timely continuation of R&D programs relying on Ethernet 1000 Base-T and SFP 1000 Base-X for command and control.
Senior Fpga Firmware Engineer
- Designed FPGA Firmware components in an R&D setting which bolstered and moved forward Raytheon’s design reuse efforts for their Electronic Surveillance and Electronic Attack products. These components speed FGPA.
- Reverse engineered legacy Electronic Attack FPGA hardware and performed hardware integration and testing. Work on legacy FPGA Firmware for Raytheon Electronic Attack and Electronic Surveillance products supported the.
- Led and mentored a small R&D team of junior Firmware Engineers to design and develop a sea based Electronic Attack Digital Signal processor in addition to Firmware development duties.
- Successfully planned engineering development schedule which specified team tasking and task dependencies to aide in the Firmware Lead role.
- As the subject matter expert regarding System-On-Chip (SoC) FPGA’s, collaboratively worked with fellow FGPA engineers to design, develop, and test F-18 Electronic Warfare designs on beta level Xilinx chips.
Systems Engineer Iii
- Worked with the Electrical Design and Integration (EDI) team to integrate and test the HEO4 payload during Thermal Vacuum Chamber Testing.
- Analyzed and presented payload test data to representatives of Lockheed Martin, Aerospace Corporation, and U.S. Air Force during Customer Data Reviews.
- Collaborated with the EDI team and Senior Staff during HEO4 Failure Review Boards. This involved directly testing and analyzing the payload in cleanroom conditions to find failure root cause.
- Represented Northrop Grumman at Sierra Nevada Corporation in Boulder, Colorado during an FRB investigation to dissect a failed component. My observations directly informed senior staff and allowed for next steps in the.
- Reverse Engineered the design of the Special Sensor Microwave Image/Sounder (SSMIS) Simulator STE and used that information to design the new simulator which is currently in service and is used to verify SSMIS Flight.
- Utilized PTC Creo solid modeling software to perform the Mechanical design and Zuken E3 in order to perform the Electrical Wiring design of the SSMIS Simulator’s Interconnect Box Assembly. This design was successfully.
Systems Engineer Ii
- Worked with the Electrical Design and Integration (EDI) team to integrate and test the HEO4 payload during Thermal Vacuum Chamber Testing.
- Analyzed and presented payload test data to representatives of Lockheed Martin, Aerospace Corporation, and U.S. Air Force during Customer Data Reviews.
- Collaborated with the EDI team and Senior Staff during HEO4 Failure Review Boards. This involved directly testing and analyzing the payload in cleanroom conditions to find failure root cause.
- Represented Northrop Grumman at Sierra Nevada Corporation in Boulder, Colorado during an FRB investigation to dissect a failed component. My observations directly informed senior staff and allowed for next steps in the.
- Reverse Engineered the design of the Special Sensor Microwave Image/Sounder (SSMIS) Simulator STE and used that information to design the new simulator which is currently in service and is used to verify SSMIS Flight.
- Utilized PTC Creo solid modeling software to perform the Mechanical design and Zuken E3 in order to perform the Electrical Wiring design of the SSMIS Simulator’s Interconnect Box Assembly. This design was successfully.
Electrical Systems Engineer
- Collaborated in an Engineering R&D team to design and develop 3D scanning equipment used by production to improve in-house dental crown fabrication and save on material costs. - Designed mechanical system for 3D scanner to allow 3D sensors to observe objects at multiple angles with design simplicity and cost being major factors in design. - Developed.
Mechanical Engineer
- Collaborated in an Engineering R&D team to design blood glucose sensing medical devices worn by patients worldwide.
- Designed tooling and fixtures which support and improved assembly processes of Medtronic products.
- Designed automated testing equipment controlled with National Instruments data acquisition hardware and Labview. Testing equipment delivered vital failure mode data to Medtronic Product Designers.
- Employed the use of Solidworks, Machining, Injection Molding, and Stereo lithography Rapid Prototyping in order to design, analyze, and fabricate tooling that supported the glucose sensor manufacturing line.
- Performed testing and analysis on sensor devices in order to solve device failure.
- Successfully identified inconsistencies in the assembly processes which caused device failure and proved that enhancements would prevent similar failure in the future.
Student
Associate Engineer
General Physics Corporation (www.gpworldwide.com)Chatsworth, CA, June 2008 to June 2009Engineering services company providing design and inspection of pressure vessel and piping systems for the aerospace industry. Clients include companies such as United Technologies Corporation, Boeing, and TIMET. Associate Engineer - Selected to aid in the completion of.
Engineering Draftsman
Sky Rider Equipment Company (www.sky-rider.com)Anaheim, CA, May 2007 to May 2008Manufacturer of standard and custom high rise access equipment for use in the cleaning or painting of a building's exterior. Currently services 200 buildings in the states of California, Nevada, and Arizona.Engineering Draftsman- Demonstrated quick learning ability when in a.
Mark Espinosa education
Masters In Electrical Engineering, Robotics And Computer Engineering
Bachelor Of Science, Mechanical Engineering
Bio-Molecular Science
High School Diploma, Health Care Professions Magnet School
Frequently asked questions about Mark Espinosa
Quick answers generated from the profile data available on this page.
What company does Mark Espinosa work for?
Mark Espinosa works for Raytheon Intelligence & Space.
What is Mark Espinosa's role at Raytheon Intelligence & Space?
Mark Espinosa is listed as Senior FPGA Firmware Engineer at Raytheon Intelligence & Space.
What is Mark Espinosa's email address?
AeroLeads has found 1 work email signal at @ngc.com for Mark Espinosa at Raytheon Intelligence & Space.
What is Mark Espinosa's phone number?
AeroLeads has found 11 phone signal(s) with area code 714, 909, 703 for Mark Espinosa at Raytheon Intelligence & Space.
Where is Mark Espinosa based?
Mark Espinosa is based in Mckinney, Texas, United States while working with Raytheon Intelligence & Space.
What companies has Mark Espinosa worked for?
Mark Espinosa has worked for Raytheon Intelligence & Space, Northrop Grumman, Glidewell Laboratories, Medtronic, and California State University Fullerton.
How can I contact Mark Espinosa?
You can use AeroLeads to view verified contact signals for Mark Espinosa at Raytheon Intelligence & Space, including work email, phone, and LinkedIn data when available.
What schools did Mark Espinosa attend?
Mark Espinosa holds Masters In Electrical Engineering, Robotics And Computer Engineering from California State Polytechnic University-Pomona.
What skills is Mark Espinosa known for?
Mark Espinosa is listed with skills including Mechatronics, Solidworks, Pro/Engineer, Labview, C++, Matlab, Precision Machining, and Metal Fabrication.
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