Mark Espinosa Email & Phone Number
@ngc.com
11 phones found area 714, 909, and 703
LinkedIn matched
Who is Mark Espinosa? Overview
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Mark Espinosa is listed as Senior Firmware Engineer at Sierra Nevada Corporation, a with 4798 employees, based in Mckinney, Texas, United States. AeroLeads shows a work email signal at ngc.com, phone signal with area code 714, 909, 703, and a matched LinkedIn profile for Mark Espinosa.
Mark Espinosa previously worked as Senior FPGA Firmware Engineer at Raytheon Intelligence & Space and Senior FPGA Firmware Engineer at Raytheon Intelligence & Space. Mark Espinosa holds Masters In Electrical Engineering, Robotics And Computer Engineering from California State Polytechnic University-Pomona.
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About Mark Espinosa
FPGA Firmware Engineer with excellent independent professional judgment. Can successfully perform professional engineering assignments while applying engineering principles, theories, and concepts. Currently has experience in Research and Development (R&D) and Systems Engineering teams and is able to innovate conceptual designs and perform analysis for both Mechanical and Electrical Systems. Is able to work efficiently in a team or independently. Specialties: FPGA Development | RTL Design and simulation | Hardware Integration and Testing | Analysis and Testing | ESD and Cleanroom Hardware environments | Meeting Critical Deadlines | Team Leadership and Collaboration | Client Relations & Presentation |Core: Xilinx Vivado and ISE, VHDL, Verilog, Mentor Graphics Questasim and Modelsim, Python scripting, C++, Matlab, Simulink, Synopsis SynolifyOther: Fusion 360, Simplify3D, Mathcad, Labview, AutoCAD, Solidworks, Pro-E, Machine Shop, Labview, Pro-Engineer, PSPICE
Listed skills include Mechatronics, Solidworks, Pro/Engineer, Labview, and 46 others.
Mark Espinosa's current company
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Mark Espinosa work experience
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Senior Fpga Firmware Engineer
Senior Fpga Firmware Engineer
• Successfully performed Ethernet integration & testing on Xilinx Artix7 AC701 and Virtex UltraScale+ VCU118 evaluation boards. Integration activities employed the used of Vivado Logic Analyzer, Wireshark, Python scripts, and an in house custom UDP protocol. • Integration allowed for the timely continuation of R&D programs relying on Ethernet 1000 Base-T and SFP 1000 Base-X for command and control.
Senior Fpga Firmware Engineer
• Designed FPGA Firmware components in an R&D setting which bolstered and moved forward Raytheon’s design reuse efforts for their Electronic Surveillance and Electronic Attack products. These components speed FGPA Firmware development for Raytheon to develop products faster. • Reverse engineered legacy Electronic Attack FPGA hardware and performed hardware integration and testing. Work on legacy FPGA Firmware for Raytheon Electronic Attack and Electronic Surveillance products supported the Air Force’s desire to reuse legacy hardware. • Led and mentored a small R&D team of junior Firmware Engineers to design and develop a sea based Electronic Attack Digital Signal processor in addition to Firmware development duties. • Successfully planned engineering development schedule which specified team tasking and task dependencies to aide in the Firmware Lead role. • As the subject matter expert regarding System-On-Chip (SoC) FPGA’s, collaboratively worked with fellow FGPA engineers to design, develop, and test F-18 Electronic Warfare designs on beta level Xilinx chips.
Systems Engineer Iii
• Worked with the Electrical Design and Integration (EDI) team to integrate and test the HEO4 payload during Thermal Vacuum Chamber Testing. • Analyzed and presented payload test data to representatives of Lockheed Martin, Aerospace Corporation, and U.S. Air Force during Customer Data Reviews. • Collaborated with the EDI team and Senior Staff during HEO4 Failure Review Boards. This involved directly testing and analyzing the payload in cleanroom conditions to find failure root cause.• Represented Northrop Grumman at Sierra Nevada Corporation in Boulder, Colorado during an FRB investigation to dissect a failed component. My observations directly informed senior staff and allowed for next steps in the project to be taken. • Reverse Engineered the design of the Special Sensor Microwave Image/Sounder (SSMIS) Simulator STE and used that information to design the new simulator which is currently in service and is used to verify SSMIS Flight Software. • Utilized PTC Creo solid modeling software to perform the Mechanical design and Zuken E3 in order to perform the Electrical Wiring design of the SSMIS Simulator’s Interconnect Box Assembly. This design was successfully fabricated, assembled and is in service. • Collaborated with Hardware Engineering to create the FPGA Verification Plan for the JPL Orbiting Carbon Observatory 3 (OCO3) project. • Implemented the VHDL design of a Complimentary Median Filter (CMF) Algorithm for the OPIR IRAD ESPA project to filter Infrared Scanner imagery being received by a Virtex 5 FPGA Node. • Designed and Implemented FPGA Node designs for the OPIR IRAD ESPA to serve a variety of functions. These include nodes designs which perform Wideband Downlink, Narrowband Downlink and PCA Simulator functionality. • Designed and Implemented a relay node using the Actel Proasic3e FPGA utilizing the Actel Libero environment.
Systems Engineer Ii
• Worked with the Electrical Design and Integration (EDI) team to integrate and test the HEO4 payload during Thermal Vacuum Chamber Testing. • Analyzed and presented payload test data to representatives of Lockheed Martin, Aerospace Corporation, and U.S. Air Force during Customer Data Reviews. • Collaborated with the EDI team and Senior Staff during HEO4 Failure Review Boards. This involved directly testing and analyzing the payload in cleanroom conditions to find failure root cause.• Represented Northrop Grumman at Sierra Nevada Corporation in Boulder, Colorado during an FRB investigation to dissect a failed component. My observations directly informed senior staff and allowed for next steps in the project to be taken. • Reverse Engineered the design of the Special Sensor Microwave Image/Sounder (SSMIS) Simulator STE and used that information to design the new simulator which is currently in service and is used to verify SSMIS Flight Software. • Utilized PTC Creo solid modeling software to perform the Mechanical design and Zuken E3 in order to perform the Electrical Wiring design of the SSMIS Simulator’s Interconnect Box Assembly. This design was successfully fabricated, assembled and is in service. • Collaborated with Hardware Engineering to create the FPGA Verification Plan for the JPL Orbiting Carbon Observatory 3 (OCO3) project. • Implemented the VHDL design of a Complimentary Median Filter (CMF) Algorithm for the OPIR IRAD ESPA project to filter Infrared Scanner imagery being received by a Virtex 5 FPGA Node. • Designed and Implemented FPGA Node designs for the OPIR IRAD ESPA to serve a variety of functions. These include nodes designs which perform Wideband Downlink, Narrowband Downlink and PCA Simulator functionality. • Designed and Implemented a relay node using the Actel Proasic3e FPGA utilizing the Actel Libero environment.
Electrical Systems Engineer
- Collaborated in an Engineering R&D team to design and develop 3D scanning equipment used by production to improve in-house dental crown fabrication and save on material costs. - Designed mechanical system for 3D scanner to allow 3D sensors to observe objects at multiple angles with design simplicity and cost being major factors in design. - Developed belt driven rotary actuator to position scanner objects exactly in the center of the sensor scan range. Rotary actuator was a custom solution which allowed for scanning freedom and accuracy. - Designed mechanical parts and fixtures using Solidworks 2013, Rapid Prototyping, and Machining knowledge used on automated scanning machinery. - Utilized the C# programming language to develop engineering graphical user interface to control motion systems and 3D scanners. Interface greatly aided the development of automated scanning equipment.- Used the C++ programming language to write programs which parsed raw point cloud data from 3D scanning hardware. Programs enabled engineering team to use scan data and assess scanning strategies.- Specified and designed electrical architecture for use in a portable hand held 3D scanning system. - Used Cadsoft Eagle to quickly design basic PCB circuit boards for prototyping applications. - Interfaced with Aptina CMOS image sensors using I2C communication protocol in order to extract 10-bit pixel data. Data allowed for the performance of image sensors to be assessed for 3D scanning solutions.
Mechanical Engineer
• Collaborated in an Engineering R&D team to design blood glucose sensing medical devices worn by patients worldwide.• Designed tooling and fixtures which support and improved assembly processes of Medtronic products. • Designed automated testing equipment controlled with National Instruments data acquisition hardware and Labview. Testing equipment delivered vital failure mode data to Medtronic Product Designers. • Employed the use of Solidworks, Machining, Injection Molding, and Stereo lithography Rapid Prototyping in order to design, analyze, and fabricate tooling that supported the glucose sensor manufacturing line.• Performed testing and analysis on sensor devices in order to solve device failure. • Successfully identified inconsistencies in the assembly processes which caused device failure and proved that enhancements would prevent similar failure in the future.• Supervised and directed R&D clean room assembly line to ensure proper methods and processes were used.
Student
Associate Engineer
General Physics Corporation (www.gpworldwide.com)Chatsworth, CA, June 2008 to June 2009Engineering services company providing design and inspection of pressure vessel and piping systems for the aerospace industry. Clients include companies such as United Technologies Corporation, Boeing, and TIMET. Associate Engineer - Selected to aid in the completion of G.P. contracts requiring the ability to rapidly change rolls. - Given a lot of responsibility, very quickly, and with little supervision. I thrived in this environment accomplishing projects on schedule and to the client’s satisfaction. - Placed as General Physics Corp. only on-site Contractor to Boeing’s Santa Susana Field Laboratory. - Successfully coordinated with Boeing, N.A.S.A., and CH2MHill staff to oversee the preparation and extraction of 170,000 lb Nitrogen pressure vessels. - Completed cataloging and shipping equipment to N.A.S.A. sites Marshall and Stennis two weeks ahead of schedule while managing trucking and rigging crews. - Innovatively used AutoCAD’s 3D capabilities to create isometric drawings of Piping and Identification (P&ID) systems. This enabled TIMET Plant Engineers to locate Ultrasonic Pipe inspection points easily. The Plant Engineers were very pleased and wanted more drawings of other systems. My work boosted my company’s image with the TIMET Plant Engineers. - Testimonial: “Mark worked for us and did a fine job of it” – Jim Gill (Principle Engineer)
Engineering Draftsman
Sky Rider Equipment Company (www.sky-rider.com)Anaheim, CA, May 2007 to May 2008Manufacturer of standard and custom high rise access equipment for use in the cleaning or painting of a building's exterior. Currently services 200 buildings in the states of California, Nevada, and Arizona.Engineering Draftsman- Demonstrated quick learning ability when in a few days learned AutoCAD Mechanical Desktop software to perform everyday duties. My supervisors were very pleased at the speed the required program was learned. My company was able to move forward with projects quicker than anticipated.- Effectively reviewed Architectural and Structural drawings to determine building structural configuration. Identified structural trusses and I-beams on building roof top where davit pedestals could be mounted. - Collaborated with design team to determine optimal placement of davit pedestals. Forces asserted on Truss and I-beam structures and davit boom reach were accounted for. - Consistently observed California law when determining placement. - Improved on proposed equipment placements to account for overlooked building configurations. - Utilized AutoCAD Mechanical Desktop to modify and design davits and pedestals in order to tailor existing equipment to client needs. - Designed a scaffolding system for a Hydraulic Telescoping Crane. My company was then able to mount the crane at the required height to complete the project on time.
Colleagues at Sierra Nevada Corporation
Other employees you can reach at sncorp.com. View company contacts for 4798 employees →
Kip Blackwell
Colleague at Sierra Nevada CorporationColorado Springs, Colorado, United States
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Joshua Alvarado
Colleague at Sierra Nevada CorporationReno, Nevada, United States
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Nicole Robinson
Colleague at Sierra Nevada CorporationGreater Reno Area, United States
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Bijan Roy
Colleague at Sierra Nevada CorporationSterling, Virginia, United States
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Chip Gregory
Colleague at Sierra Nevada CorporationDenver, Colorado, United States
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Connor London
Colleague at Sierra Nevada CorporationGreater Reno Area, United States
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Susan Dalluhn/Snc/Sncorp
Colleague at Sierra Nevada CorporationSparks, Nevada, United States
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Jenny Lund
Colleague at Sierra Nevada CorporationSparks, Nevada, United States
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Gary Radish
Colleague at Sierra Nevada CorporationThe Villages, Florida, United States
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Brad Killebrew
Colleague at Sierra Nevada CorporationMonument, Colorado, United States
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Mark Espinosa education
Masters In Electrical Engineering, Robotics And Computer Engineering
Bachelor Of Science, Mechanical Engineering
Bio-Molecular Science
High School Diploma, Health Care Professions Magnet School
Frequently asked questions about Mark Espinosa
Quick answers generated from the profile data available on this page.
What company does Mark Espinosa work for?
Mark Espinosa works for Sierra Nevada Corporation.
What is Mark Espinosa's role at Sierra Nevada Corporation?
Mark Espinosa is listed as Senior Firmware Engineer at Sierra Nevada Corporation.
What is Mark Espinosa's email address?
AeroLeads has found 1 work email signal at @ngc.com for Mark Espinosa at Sierra Nevada Corporation.
What is Mark Espinosa's phone number?
AeroLeads has found 11 phone signal(s) with area code 714, 909, 703 for Mark Espinosa at Sierra Nevada Corporation.
Where is Mark Espinosa based?
Mark Espinosa is based in Mckinney, Texas, United States while working with Sierra Nevada Corporation.
What companies has Mark Espinosa worked for?
Mark Espinosa has worked for Sierra Nevada Corporation, Raytheon Intelligence & Space, Northrop Grumman, Glidewell Laboratories, and Medtronic.
Who are Mark Espinosa's colleagues at Sierra Nevada Corporation?
Mark Espinosa's colleagues at Sierra Nevada Corporation include Kip Blackwell, Joshua Alvarado, Nicole Robinson, Bijan Roy, and Chip Gregory.
How can I contact Mark Espinosa?
You can use AeroLeads to view verified contact signals for Mark Espinosa at Sierra Nevada Corporation, including work email, phone, and LinkedIn data when available.
What schools did Mark Espinosa attend?
Mark Espinosa holds Masters In Electrical Engineering, Robotics And Computer Engineering from California State Polytechnic University-Pomona.
What skills is Mark Espinosa known for?
Mark Espinosa is listed with skills including Mechatronics, Solidworks, Pro/Engineer, Labview, C++, Matlab, Precision Machining, and Metal Fabrication.
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