Mark Patterson Email & Phone Number

Los Angeles, Ca, Us

Westlake Village, California, United States

Westlake Village, California, United States

Design and development of microelectronic packaging for telecom, storage, and embedded processor applications. Developed new flip-chip, wirebond, and MCM products using high density build-up, laminate, and ceramic substrate technologies. Working with subcontractors on substrate design and assembly. Design and verification of 10Gb/s and faster substrates using simulation and measurement. Analyzing signal integrity issues including high speed design, SSN, and power supply stability.Electrical simulation: Responsible for all aspects of package signal integrity, daily experience with modeling tools including Ansoft HFSS, TPA, Q3D, SIWave, Designer, Sigrity PowerSI,and Cadence APD.Thermal simulation: Working within system confines to meet heat dissipation targets and device temperature specs. Defining thermal management specifications such as airflow and heat sinking at package and board level. Mechanical FEA modeling of package and board level stress.

Design of high frequency ceramic and organic packaging for narrowband microwave and mm-wave products and wideband digital applications. Worked with customers to define electrical and mechanical requirements on new commercial and military products. Customers included Northrup Grummen, Lockheed Martin, TRW, and Boeing. Used Ansoft and Agilent EM software to optimize package performance. Modeled die to package and package to board interactions for sensitive applications. Verified electrical performance through measurement on vector network analyzer. Presented simulation and measurement data to customers as part of project packaging proposal.

M.S., Thermal Sciences

Activities and Societies: Phi Kappa Phi

B.S., Mechanical Engineering