Technical Manager
Current
Formerly Intel, Amd, Hp
2000 - Present
~26 yrs 7 mos
AeroLeads people directory · profile
Mark Laser Email & Phone Number
Engineering Manager Leading International Design Teams
at
Formerly Intel, AMD, HP
1 work email found
@intel.com
2 phones found area 408
LinkedIn matched
✓ Verified August 2026
4 data sources
Profile completeness 100%
Current company
Formerly Intel, AMD, HP
Role
Engineering Manager Leading International Design Teams
Location
Montrose, Colorado, United States
Who is Mark Laser? Overview
A concise factual answer block for searchers comparing this professional profile.
Quick answer
Mark Laser is listed as Engineering Manager Leading International Design Teams at Formerly Intel, AMD, HP, based in Montrose, Colorado, United States. AeroLeads shows a work email signal at intel.com, phone signal with area code 408, and a matched LinkedIn profile for Mark Laser.
Mark Laser previously worked as Technical Manager at Formerly Intel, Amd, Hp and Validation Manager at Intel Corporation. Mark Laser holds Bachelor Of Science (Bs), Engineering from California Polytechnic State University-San Luis Obispo.
Company email context
Email format at Formerly Intel, AMD, HP
This section adds company-level context without repeating Mark Laser's masked contact details.
{first}.{last}@intel.com
86% confidence
AeroLeads found 1 current-domain work email signal for Mark Laser. Compare company email patterns before reaching out.
Profile bio
About Mark Laser
Leading teams designing pre-si to PRQ Power Management validation strategy and execution for Intel SoC.Creates, defines and develops system validation environment and test suites. Uses and applies emulation and platform-level tools and techniques to ensure performance to spec. Responsible for the development of methodologies, execution of validation plans, and debug of failures. Broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features. Engaged in the use of pre-si techniques such as SLE, CSLE, HSLE, HFPGA, Simics and silicon for system validation and Power Management.Pre-Post Silicon System Validation Architect with experience as an Individual Contributor and Technical Manager, specializing in design and execution of New IP validation techniques. Possessing a unique combination of strong, diverse technical skills focusing on customer satisfaction. Career encompasses System Validation design for New Product Introduction/New Technology, Lead Platform Validation Design Engineer, Management of Asian validation test teams, System Performance, bug resolution, lead for intensive debug teams and principal lead for training International teams. Recognized for excellent customer service skills and the ability to understand complex technical situations and provide creative solutions.Worldwide experience in Power Station/Gas Compression Construction using Industrial Gas Turbines. PLC Control system experience. Solar Turbine Gas Turbines products including Saturn, Centaur, Taurus, Mars. Power Generation product experience with Generators, Switchgear, Protection and Condition Monitoring. Specialties: Computer Systems:System ValidationProduct Lead Platform Test EngineerManagement of test teamsSystem PerformanceLead for bug investigationsTraining International teams
Listed skills include Testing, Program Management, Debugging, Software Development, and 46 others.
Current workplace
Mark Laser's current company
Company context helps verify the profile and gives searchers a useful next step.
Formerly Intel, Amd, Hp
13 roles · 45 years
Mark Laser work experience
A career timeline built from the work history available for this profile.
Validation Manager
Manage teams which creates, defines and develops system validation environment and test suites. Uses and applies emulation and platform-level tools and techniques to ensure performance to spec. Responsible for the development of methodologies, execution of validation plans, and debug of failures. Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features.
Aug 2014 - Jan 2018
System Validation Architect
Pre/Post silicon System Validation Architect for PC Client platforms using Simics and HFPGA for system validation in pre-silicon achieving post silicon schedule compression.
Sep 2013 - Aug 2014
Senior System Debug Manager
Jul 2013 - Aug 2014
System Validation Architect
System Level Validation Engineer leading a validation development teams in a variety of functional validation Test Planning and Test Methodologies, including system, and various sub systems such as Power Management, Video, Memory, Core, OS/Apps, hardware analysis tools and traffic/load analysis tools
Aug 2009 - Jul 2013
Technical Manager/Individual Contributor, System Validation Architecture
Silicon system validation design, System Validation Architect, Technical Manager
Jul 2009 - Jul 2013
Research And Development Engineer
Validation Engineer for New Product Development with Workstation products.
Feb 2006 - Jul 2009
Manager Program Management
MANAGER — PROGRAM MANAGEMENTManager responsible for international and domestic projects for Gas Turbine and Reciprocating Power Generation Control systems
2005 - 2006
~1 yr
Open Source Program Manager
Hewlett Packard - Linux Open Source Lab
Program Manager responsible for use of Open Source Software on HP equipment Worldwide.
2004 - 2005
~1 yr
Systems Performance Engineer
Engineer responsible for performance of Independent Software vendors in CAD, CAE and GIS, platform maintenance, platform performance and competitive evaluation. Recognized for diligence in resolving international customer issues while teaming with Independent Software Vendors and Hewlett Packard engineers.• Experience with IA-64/IA-32/PA-Risc/Power4/Power3/Ultra-Sparc server/workstation platforms• Operating Systems include Linux, Unix (HP-UX/AIX/Solaris), Windows• Support for Customer installations of Linux/Unix/Windows for GIS, CAD, CAE applications• Managed Benchmark Lab performing hardware analysis, software performance• Prototype hardware/software testing and troubleshooting• Java, C++, Unix scripting
1998 - 2004
~6 yrs
Country Director - Venezuela
Unc Industrial Power
Senior Field Engineer/Project Manager/Country Manager for South America responsible for the design, construction, installation and startup of utility power plants and natural gas compression installations. Project Engineer for the design of PLC controls for gas turbine packages. Responsible for the yearly sales quotas, expense control and in-country employees.• Program Manager for multiple International Customers• Management of multiple products across life-cycle• Project Management of new products based on evolving industries• Design of Programmable Logic Controller System for utility industry• Domestic and International Subcontract Management for multi-million dollar projects• Estimating and Negotiating Customer Projects• Yearly 200% growth in South American business during tenure
1995 - 1998
~3 yrs
Program Manager
Responsible for international and domestic projects, design of retrofit PLC Control systems and Program Manager for development and introduction of new products to industry. Known for excellent life cycle Program Management skills. Recognized with a number of patents.• Program Manager product design, sales and installation• Design of Retrofit Programmable Logic Controller System• Management of Alternate Fuel systems for Gas Turbines• Failure Analysis of Gas Turbine Packages• Computer Controlled Low Emissions development for Gas Turbine engines
1985 - 1995
~10 yrs
Failure Analysis Engineer
Failure Analysis engineer working on the Space Shuttle, Atlas Launch Vehicle, and Cruise Missile programs.• Materials Engineer Assigned to Centaur Program• Failure Analysis engineer for program• Materials Specialist for Avionics packages for space application• Development of Carbon fiber materials for space use
1982 - 1985
~3 yrs
4 education records
Mark Laser education
Bachelor Of Science (Bs), Engineering
Computer Science
Education record
Francis Parker
Engineering
Coursera
FAQ
Frequently asked questions about Mark Laser
Quick answers generated from the profile data available on this page.
What company does Mark Laser work for?
Mark Laser works for Formerly Intel, AMD, HP.
What is Mark Laser's role at Formerly Intel, AMD, HP?
Mark Laser is listed as Engineering Manager Leading International Design Teams at Formerly Intel, AMD, HP.
What is Mark Laser's email address?
AeroLeads has found 1 work email signal at @intel.com for Mark Laser at Formerly Intel, AMD, HP.
What is Mark Laser's phone number?
AeroLeads has found 2 phone signal(s) with area code 408 for Mark Laser at Formerly Intel, AMD, HP.
Where is Mark Laser based?
Mark Laser is based in Montrose, Colorado, United States while working with Formerly Intel, AMD, HP.
What companies has Mark Laser worked for?
Mark Laser has worked for Formerly Intel, Amd, Hp, Intel Corporation, Amd, Hewlett-Packard, and Encorp.
How can I contact Mark Laser?
You can use AeroLeads to view verified contact signals for Mark Laser at Formerly Intel, AMD, HP, including work email, phone, and LinkedIn data when available.
What schools did Mark Laser attend?
Mark Laser holds Bachelor Of Science (Bs), Engineering from California Polytechnic State University-San Luis Obispo.
What skills is Mark Laser known for?
Mark Laser is listed with skills including Testing, Program Management, Debugging, Software Development, Engineering, Embedded Systems, Cross Functional Team Leadership, and Product Development.
Find 750M verified contacts
Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.
Start free trialPeople with similar names
Check these profiles if this is not the Mark Laser you were looking for.
View similar profiles
