〓 To operate & run Automated Optical Inspection (AOI) machine in production line〓 Multitasking in support to production related functions eg, coordinate meetings to inform defect findings and work along to resolves issues〓 Perform wafer offline review accurately〓 Understand all the AOI defect code, common bin for each AOI process – how it look like and the root cause

• Liaise with Purchasing Department for any material quality issues and follow up• Update all calibrations and Preventive Maintenance for equipment and instruments• To perform disposition based on the results of the incoming inspection• Perform RMA from customer returns. • Prepare Test Report after a completion of every SO or when there is delivery schedule• Comply with all quality, safety, and work rules and regulation• Document control - upload all specs provided by respective departments and file accordingly• Handling of QA Inspectors: Plan & manage the schedule of QA inspectors• Buy off/inspection of FG's with reference to product specifications

Job PurposeOverall responsible for the quality of products from incoming, stock to end customer.Principal Responsibilities• Ensure calibration and maintenance is performed on inspection equipment.• Comply with all quality, safety, and work rules and regulations• Audit and monitor quality requirements in accordance with the company quality assurance policies and customer specifications.• Assist in maintaining QMS.(Document Controller)• Support and participate 2nd & 3rd party audit • Prepare monthly report for quality.• Assist production in Quality improvement.• Assist in raising PR for quality.• Perform other miscellaneous duties as assigned by HODAuthority• Issue outgoing report or COC.• Issue NCR & 8D Report to supplier or internal company.• To stop operation of machine if conditions are out of safety measures or not able to achieve specified process / operation conditions.

Handle complaints from customers' feedbackResponse to customers feedback and complains.Analyze the Products' complaints failure mechanism and separate them in various categories and trend them into statistical ChartCompile and document all complaints daily to feedback and drive continuous quality improvement in conjunction with engineering, failure analysis and operations.Assist management in development of Quality Program Plan(s) for subsequent revisions.Perform adequacy reviews for flow down of QA requirements to implementing documents and quality affecting processes.

Product Engineer (Technology Development)1/07/2009 to 31/07/2013Working with Fab integration, Module, EWS testing, FA, Planning, and Back-End team to conduct process improvement, and solve product issues.Production lots yield monitoring, analysis, and disposition.Involving in yield improvement of device DOE tuning, split trial.Setup Wafer level EWS and Package level FT test flow and limits. Manage Skip Test for cost reduction.In charge of IM and HTOL Reliability test on QFP packaged product qualification of test chips.Analyzing WAT, CP, inline data to deal with low yield and improve yield by means of tool commonality, SPC, FMEA, etc.Quality assurance check. Manage Statistic Bin Limit and PPAT to control product Quality. Responsible for new product introduction, from Codification, Mask order, RD lots planning, EWS qualification, until Stop Commitment; Manage procedure from Substrate/Semiwafer/Wafer/Die/FEP/Raw line/Finished Goods/Commercial Products. Handling Package product complain and low yield issue failure analysis and disposition, investigating assembly and testing issues. Lead projects/programs, like FEOL process change, new EWS site qualification, tester qualification, etc. Characterization and debug of package by using ATE (Spea) and semi-ATE (Tesec).Tools and software: ACE XP, JMP, Tesec tester, Spea tester, Galaxy, Finder, STIF Analyzer, CLS, PRIS, TIS, etcFailure Analysis Engineer (Technology Development)26/06/2000 to 1/07/2009Physical and Electrical Failure Analysis on chips and packages of prototype products from 8 inch 240nm Al/Cu technology down to 12 inch 65nm Cu technology nodes. Familiar with SEM, Nanoprobing system, FIB, PEM, OBIRCH, TIVA, sample polishing tools, plasma etching and chemical deprocessing etc.9-month (Nov. 2005 to August 2006) Joint Development Approach Project with IBM Microelectronics, Fishkill, NY, US.

• Clean room environment in term of clean room protocol, routine audit, particle investigation to trouble shoot the root cost of count whenever they is high particle count and submit daily report • Ensure all daily routine quality procedure are being follow up as a leader to the night shift quality issues in terms of decision making toward the follow up clean room procedures• Control equipment calibration procedure and liaise with vendors to generate a calibration report for equipment such as particle counter, oscilloscope and temperature logger (thermal couple)