Marwan Mohamad Email and Phone Number

Project Assignment: AMD LSIO FV on AMD EPYC Server PlatformPLT Serv Sys Val-PNGDevelop and improve validation test plan (methodology, test strategy) for LSIO team coverage.Develop post silicon infrastructure.Execute feature enablement from the test planeSPI Boot (up to 66Mhz coverage)eSPI SAFS Boot (Hardware Mode, Mixed Mode, Software Mode)I2C/I3C (Telemetry Test)SPI UARTGPIOWith the usage of conventional Keysight/Tektronix scope + Beagle/Aardvark Team also been using Acute MSO3000 as an alternative for above scope/equipment as it offers more information to help validation teamResponsible to drive customer/internal ticket by running design of experiment and updating the PLAT with findings and recommendation. Work across many different BU/department (Firmware, BIOS team) to root caused issue and closed the ticket

PSG (Programmable Solution Group)PSE PPSE PVE MY EV5 EMIF-EV Team (External Memory Interface)Work on Intel FPGA product on Pre and Post Silicon Validation covering RX/TX/Regulator. Electrical/Timing/Training validation covering DDR5, DDR4, LPDDR5 and LPDDR4 IO standardFamiliar with equipment/software related to EV environment:Keysight/LeCroy/Tektronix OscilloscopeBERT scopeDigital MultimeterPattern GeneratorPower SupplyPython/Spyder/Anaconda

Senior Validation Engineer for NSG Group (NAND Solution Group) at INTEL KM3 to validate and perform sanity check on electrical design, related to product requirement document using worst case voltage and temperature condition on typical silicon processes.Electrical validation and signal integrity validation for product based on SATA, PCIe, M2 & SASElectrical Validation - Power Up Sequence, Power Down Sequence, Crystal Characterization, PLI Crossover, Current Measurement, Voltage Measurement, SDRAM Timing Margin, NAND Timing Margin, Operating Limits, Power Cycle, power rail short & etcSignal Integrity - SPI, I2C, SMBus, NAND SI, DRAM SI, Media SI(Optane)

First Solar Kulim as a programmer to restructure PLC Ladder diagram.INTEL Kulim (KM2) as 2nd level debug Engineer.

Validation Engineer at INTEL PG2-Post silicon validation (USB2 Interface)