Maria Sable Email & Phone Number
@marvell.com
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Who is Maria Sable? Overview
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Maria Sable is listed as Memory Subsystem Verification Engineer at AMD, a with 44382 employees, based in Raleigh, North Carolina, United States. AeroLeads shows a work email signal at marvell.com and a matched LinkedIn profile for Maria Sable.
Maria Sable previously worked as Senior Staff Design Verification Engineer at Marvell Technology and Staff Design Verification Engineer at Marvell Technology. Maria Sable holds Master'S Degree, Computer Engineering from North Carolina State University.
Email format at AMD
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AeroLeads found 1 current-domain work email signal for Maria Sable. Compare company email patterns before reaching out.
About Maria Sable
Hi there! I'm a digital design verification engineer with 5 years of professional experience residing in the Raleigh area. I have pre-silicon verification experience with ARM AMBA protocols (AXI, APB) as well as video protocols such as DisplayPort. I have worked on networking, automotive, and video interface SoCs. In my free time, I enjoy playing board games (and teaching others to play them), reading science fiction and fantasy novels, and spending time with my standard poodle who is named after my favorite Star Trek character.
Listed skills include Testing, Systemverilog, Verilog, Universal Verification Methodology, and 13 others.
Maria Sable's current company
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Maria Sable work experience
A career timeline built from the work history available for this profile.
Senior Staff Design Verification Engineer
~ Lead block-level verification team for machine learning wrapper of networking SoC.~ Instantiate UVM environment, provide stimulus, check assertions, and scoreboard results using SystemVerilog.~ Write UVM sequences in SystemVerilog to perform register accesses utilizing AXI, ARF, and NCB protocols.~ Document DUT verification strategy, verification microarchitecture specification, and test plan using Confluence.~ Manage Git branch used by both design and verification engineers and handle merge conflicts when they arise.~ Scope out and assign tasks to other verification team members to ensure timely delivery of verification IP.
Staff Design Verification Engineer
~ Owned block-level verification for timestamp unit of automotive SoC.~ Created Confluence verification plan for DUT, from basic functionality to performance measurements.~ Instantiated UVM environment, provided stimulus, checked assertions, and scoreboarded results using SystemVerilog.~ Wrote UVM sequences in SystemVerilog to perform register reads and writes utilizing APB protocol.~ Improved nightly Jenkins regression results with Verdi to achieve functional coverage and pass rate objectives.~ Tracked discovered bugs using Jira and communicated findings with design engineers to ensure their resolution.
Digital Verification Engineer
~ Implemented environment, testbench, and tests for the DisplayPort receiver DUT using UVM in SystemVerilog.~ Improved the DisplayPort transmitter Bus Functional Model (BFM) using VMM in SystemVerilog.~ Executed plan to add ultra-high bit rate (DPv2.0) functionality to the DisplayPort receiver environment and BFM.~ Wrote test plan, enhanced functional coverage, and lead coverage reviews as block-level environment owner.~ Managed nightly regressions using Jenkins, run simulations using VCS, and debug test failures using Verdi.~ Interfaced with the digital design engineers to ensure the DUT is meeting required specifications.
Year-Round Graduate Intern
~ Programmed in JavaScript and HTML to improve the SAS Graphics Accelerator, a Chrome extension that allows blind users to listen to graphs.~ Expanded the test coverage of SAS microservices and Public REST APIs using Java and Groovy.
Undergraduate Teaching Assistant
~ Acted as an undergraduate TA for ECE 310 - Design of Complex Digital Systems.~ Ran the laboratory sessions for the course and graded student laboratory work.~ Answered student questions on block diagrams, simulation with HDL, and synthesis from RTL.
Hardware Development Test Intern
~ Assisted the project test lead with managing all hardware testing for retail point-of-sale printers.~ Performed testing of the diagnostics utility for a variety of point-of-sale devices.~ Wrote detailed defects against point-of-sale hardware for issues occurring in the field.
Itecs Help Desk Consultant
~ Provided Information Technology support for the College of Engineering.~ Assisted faculty, staff, and students with network and software issues.~ Set up and managed university-owned machines on the campus network.
Colleagues at AMD
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Maria Sable education
Master'S Degree, Computer Engineering
Bachelor'S Degree, Computer Engineering
Frequently asked questions about Maria Sable
Quick answers generated from the profile data available on this page.
What company does Maria Sable work for?
Maria Sable works for AMD.
What is Maria Sable's role at AMD?
Maria Sable is listed as Memory Subsystem Verification Engineer at AMD.
What is Maria Sable's email address?
AeroLeads has found 1 work email signal at @marvell.com for Maria Sable at AMD.
Where is Maria Sable based?
Maria Sable is based in Raleigh, North Carolina, United States while working with AMD.
What companies has Maria Sable worked for?
Maria Sable has worked for Amd, Marvell Technology, Synaptics Incorporated, Sas, and North Carolina State University.
Who are Maria Sable's colleagues at AMD?
Maria Sable's colleagues at AMD include Kuanting Lin, Sean Zhu, Michael Tucker, Jemmy Wu, and Can Turk.
How can I contact Maria Sable?
You can use AeroLeads to view verified contact signals for Maria Sable at AMD, including work email, phone, and LinkedIn data when available.
What schools did Maria Sable attend?
Maria Sable holds Master'S Degree, Computer Engineering from North Carolina State University.
What skills is Maria Sable known for?
Maria Sable is listed with skills including Testing, Systemverilog, Verilog, Universal Verification Methodology, Agile, Software Quality Assurance, Java, and C (Programming Language.
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