Mason Hix Email & Phone Number

Boise

Boise, Idaho, United States

• Use Cadence Virtuoso to design layout for DRAM and emerging memory products
• Update and create new layout based on design specs for products, depending on process
• Validate layout using tools such as LVS and DRC
• Floorplan large scale layout blocks with design considerations including signal integrity, areaconsumption, power delivery, parasitic elements, etc.
• Communicate with circuit design engineering to ensure the layout team can accommodate designrequirements, and vice versa
• Correspond with process integration to ensure drawn layout can be feasibly made in the fab

Boise, Idaho, United States

- Analyze and edit layout of NAND memory to improve ability to print onto silicon, performance of memory, and overall quality of the part.- Verify edits with LVS/DRC and communication with process team members- Double check edit areas to ensure perfection to reduce the risk of post mask edits

Boise, Idaho, United States

- Assist customers with questions about makerspace equipment- Train students, faculty, and staff how to use various makerspace equipment from start to finish. This includes equipment such as 3D printers, vinyl cutters, 3D designing, soldering iron, etc.- Troubleshoot and repair equipment when something breaks, a new part is being added, a part is being.

Boise, Idaho, United States

- Assisted in performing tests on DRAM to analyze bit failures on die and wafer level.- Learned about the structure and operation of DRAM cell, die, and wafer.- Expanded on a graphical user interface to catch failing bits from a given test and plot them on a map representing a die. - Used various testing stations to analyze bit failures at die and wafer.

Master Of Science - Ms, Electrical Engineering

Bachelor'S, Electrical And Computer Engineering