RTL reference modeling for Pre-Silicon Verification. Focused on GPU/SIMD architecture.Primary Tools: C++, Python, SystemVerilog, and a whiteboard.

- Responsible for Design Verification of new IP that dramatically improves power, area and hardware utilization of the future chip aimed at accelerating Deep Learning operations. - In a joint effort with an RTL designer, reached 100% line coverage with 100% tests passing of the new IP block in nightly regressions by writing directed tests and improving randomized testing and checking.- Automation of controlled running and post-processing results of Synopsys tools, such as Design Compiler, using Python.- Used Python to create a front-end for running and extracting data from GlobalFoundries memory macro compilers. This allowed for better experimentation of memory macro options while also bypassing the synthesis process, resulting in significantly quicker analysis of power and area data for memories in the IP.- Tools: C++, Python, Linux, Jenkins

- Used SystemVerilog to learn and improve on the structure of an existing hardware IP.- Debugged hardware code errors marked by Synopsys Spyglass.

I helped run the embedded labs with a small team of TAs. The course taught students about programming embedded software and hardware in a Linux environment. We used a Zedboard for programming in C++ and designed hardware on the board's FPGA with Matlab Simulink. The class had two design projects that enabled a robotic arm to pick and place objects.

- Research and development in controls, estimation, learning, and autonomy.- Used Python and OpenAI Gym to develop a defense-related multi-agent reinforcement learning simulation environment.- Assisted a small group with C++ programming for a game theoretic scenario.

- Summer intern. Assisted in user documentation, requirements traceability, and shell scripting with Bash.