Design and implementation of experiments to test standard Analog/Mixed signal circuit topologies in new process technology for serial link development group in ASIC organization. Determine the drawbacks and advantages of new device models and design circuits to meet specifications for future cores. Worked with architects and discussed feasibility of different topologies and helped determine a clock distribution solution.

Worked closely with the logic, timing, and integration developers to design 21 hybrid schematics and layouts using Cadence, PIP, RLM Build in the PowerPC development group. Designed circuits for power, timing, and size constraints. Tested and debugged each circuit using over 20 design rule, timing, and power analysis tools. Learned AIX, VHDL, and Cadence.