Max Kuo Email & Phone Number

台灣

Non-Volatile Engineering Transformation (NVET)• Developing media integration architecture and algorithms for Micron’s wide portfolio of system products• Provide the system solution and mitigation on the cutting edge node of the 3D NAND development for Client SSD• key creative and development roles which provide mentorship and direction to improve the overall quality Micron products by applying system and component-level expertise. • Work cross functionally, interacting with systems, component, firmware architecture• Being a proficient, dedicated authority in system integration, system debug, data gathering, and system failure analysis#Media Architect Lead for Value CSSD: 2450/2550/3460/2650#Media Architect Lead for Performance CSSD: 3500#Media Architect Lead for T700/705/500

Taiwan

• Management skill and leadership performance.• Responsible for performing failure analysis on customer returns for a specific product• Troubleshooting from system level to component level.• Interfacing with design, firmware, process, product, test and reliability engineering to solve problems.• Providing feedback and clarifies issues to customers with report.• 56/43/32/24/19/15 nm Embedded Flash ( iNAND) Test flowi. Analysis for the Data retention issue and solution with a total solution and evaluate the activation energy.ii. All the potential customer side failure mode and screen methodology during internal testing.iii. Simulation of the customer usage to cover in the internal test flow in NAND and system level.iv. NAND Failure analysis in device/testing/system point of view. ( Bit flip/ Rapid cycle/Unstable Host power)v. Implement the entire customer failure mode in the test flow with internal test team.vi. NAND BIST functional test through controller. Memory test in the system level.• 3D NAND in the BICS.• 2D NAND device functionality and operation detail with command sequence and solid state device view.• Firmware algorithm with customer host behavior analysis.

Shanghai City, China And Taiwan

• Customer OEM product test flow evaluation and determination• Wafer level reliability evaluation and failure analysis.• Package level memory technology evaluation in embedded /SD/ Special area product.• Package level testing :i. 2 years in pure NAND memory testing.ii. 3 years in testing memory with system level methodology.iii. Evaluation all the necessary screen and stress mode.• Yield improvement and RMA failure analysis.• Development of the new methodology in shorten the cycle time • One of the first creators in the memory testing by system level through controller vender command.i. Test flow coding and NAND screen development.ii. Solid NAND detail failure analysis.iii. Evaluation all the necessary screen and stress mode.

Taiwan

• New Customer device product incoming• Electrical failure analysis for low yield NOR Flash• Embedded Flash test program debug and development• KGD ( Know Good die) testing parameter control

Taiwan

• 0.18 um NOR Flash process yield improvement• EFA and PFA from the process 0.18 um to 0.5um• Embedded Flash and OTP process in the 0.18 and 0.25 node

Master Of Engineering Science, Electrical, Electronics And Communications Engineering, B

Bachelor Of Engineering (B.Eng.), Electrical, Electronic And Communications Engineering Technology/Technician, Average

Activities and Societies: Starcraft team player