Mayank Pathak Email & Phone Number

Hyderabad, Telangana, India

-- As one of the lead architects of the Blaize Picasso (SDK) I have been instrumental in several of its components as Neural Network Framework, Assembly Code Generator, LLVM backend compiler for Blaize chip, Heterogeneous C compiler etc.-- Took initiatives towards developing Regression Infrastructure, Random Test Generator etc.Fine-tuned several Deep Neural Networks for the Blaize chip.-- Was instrumental to several product decisions (such as the choice of OpenVX, LLVM cl­c++ compiler, kernel libraries, ...) in the Picasso. Also wrote technical specifications for compiler, debugger, libraries framework etc.-- Played critical role in building up the several software teams through so many interviews and campus visits; and in deliberations of processes (such as code maintenance, regressions, automotive norm ISO26262, ...).-- Proposed crucial inputs to some of the design decisions (such as size of L2 cache, L2 partitioning, more CISC ISA, ...) to the Blaize hardware architecture.

Noida, Uttar Pradesh, India

-- Initiated, designed and implemented multi­-threading in the Spyglass Concorde (RTL synthesis and optimization) engine. Parallel synthesis, with a very efficient job scheduler at core, heavily reduced the synthesis time. Making a huge legacy code base re-entrant was the major challenge.-- Developed the Technology Mapping module for sequential elements.-- Worked with improvements of various optimizations (Gate Reduction, Boundary Optimizations, ...) of the Concorde engine.

Noida, Uttar Pradesh, India

-- Ported a few modules of the old Illustrator into the new framework.

Noida Area, India

-- Improved the various heuristics (as to what amount of logic should be given) to the Clock Gating module of Concorde.-- Developed the Random Exception Generator (using interrupt mechanism within gdb) to test out the various exception handlers across all Spyglass products.-- Developed the BDD based Logic Modification Engine that modifies the RTL to fix various design violation coming from various components of the Spyglass tool­-chain.-- Developed the Transition Fault Coverage Engine (built over switching activity analysis) to estimate the controllability and observability at system frequencies. This followed after implementing a set of At­Speed design rules in the Spyglass DFT.-- Enhanced various algorithms (towards design rules), error reporting and log generation in the DFT module.

Bachelor Of Technology - Btech, Electrical, Electronics And Communications Engineering, 7.8 / 10

Senior Secondary, Physics, 91.2 %

Secondary, Science, Social Science, 93.2 %