Highly respected ASIC Design Engineer with many years of professional experience in nearly all aspects of the design flow, from device specification and RTL coding to full-chip synthesis and timing closure.Expertise in hard disk drive, network controllers and mobile communications with primary focus on all aspects of the physical implementation process on multi-million, hierarchical designs. Experience in developing new methodologies and processes for cutting edge technology nodes.Known for exceptional work ethic, scripting expertise, strong technical skills and attention to detail.Specialties: scripting, RTL design, synthesis, formal verification and static timing analysis. Emphasis on synthesis techniques, static timing and flow architecture.Extensive knowledge in Python, PERL, Tcl and UNIX shell languages.
Listed skills include Static Timing Analysis, Tcl, Asic, Timing Closure, and 13 others.