Meena Chandrasekaran Email & Phone Number

United Kingdom

Reading, England, United Kingdom

PCIe/CXL product digital chip architect

Bengaluru, Karnataka

SoC Architect for PCIe, CXL domains for Edge Computing and Accelerator products based off Intel Client and Server platforms as well as ARM Architecture SoCs.Delivered architecture definition including PCIe RP, IO Coherence, IO BW requirements and analysis, IO Virtualization, EP Accelerator SoC BAR definitions, Boot flows, Boot media flows, Rest, Power, Clocking, Low Power and Sleep state entry/exit planning, flows, estimating and meeting NIC BW requirements through Architecture decisions , CXL Type1, 2 and 3 device architecture, HDM addressing and virtualization, device cache coherence management, fuse requirements and fuse pull flows, AON FSM handshake for wake and complete SoC level PCIe/CXL domain Architecture specification for complex, multi-Die SoCs and single Die accelerator cards.Conducted various cross-domain training sessions on PCIe/ CXL and IO Virtualization during successive years as part of Learning and Development Program and Technology sessions.

Memory Subsytem Design for Tegra SOC• Memory subsystem design Lead for Tegra SoC, worked on implementing and delivering design changes related to SoC Hub and SMMU• Owned new feature definitions, RTL implementation and verification/validation support for SoC I/O Hub• Owned ARM MMU 500 configuration and delivery for integration in I/O Hub. Verification support including context and page table setup, failure debug and performance evaluation for Isochronous traffic requirements• Performed design optimizations for SoC I/O device bandwidth and latency requirements including meeting Isochronous traffic requirements via buffer sizing, TLB caching, Virtual Channels and crediting schemes• All tool-flows for ASIC RTL/netlist quality checks including Lint, CDC, Synthesis, Formal Property Verification, SLCG checks, X-propagation checks, timing fixes• Safety features including random error detection, correction and logging for ISO26262 automotive self-driving standards compliance• As Design Lead Engineer, owned milestone tracking and schedule management, task assignment to team members, conducting code, uARch, design specification reviews, verification plan review, regression tracking and triage of failures, coverage closure, mentoring new team members for coming up to speed, guiding junior engineers in team on assigned design and verification tasks

Bangalore, India

Configurable DDR Memory Controller IP design and delivery to SoC team for Qualcomm India's MSM and MDM chipsets.

Raleigh-Durham, North Carolina Area

Part of memory controller design team, involved in logic design, development and debug of front-end bus interface logic for high-performance, low-power LPDDR2/3 PCDDR3/4 memory controllers for Qualcomm's first server class chip-set at 28nm and 16nm FinFET nodes.

Raleigh-Durham, North Carolina Area

MS in Computer Engineering

Bangalore, India

MDDR controller -- Designed, developed and validated a controller for Mobile DDR- the main system memory in a dual processor connectivity solution for high-end digital cameras, for a leading Japanese camera manufacturer.-- Validated functional and cycle-level timing requirements of the Mobile DDR memory controller on a Virtex-5 FPGA based SoC prototype board at unit and system levels using the on-board Xtensa processors and DMA controller.-- Functioned as a single point of contact for all MDDR controller design related changes and implementation details throughout life-cycle.IP Design, Implementation, Verification -- Owned, implemented and validated various standard IP blocks including . DDR memory controllers . IEEE802.3 compliant 10/100/1000Mbps Ethernet MAC transmitter . USB2.0 register block, memory block and OHCI controller-- Translated protocol specifications to feature requirements and micro-architecture details.-- Handled multiple clock domains, firmware/compile-time configurability and design optimization to minimize gate count.-- Produced and maintained thorough and up-to-date technical design documents.-- Mentored junior design engineers through the design and RTL implementation process.

Ms, Computer Engineering

B.Tech., Electronics And Communication Engineering

-- Presented a paper titled "Real Time Guidance For Indoor Navigation Using Bluetooth Technology" at the 14th Annual IEEE Symposium.

High School

ASPL: Assistant School Pupil Leader, leading a school of about 3000 students, during 12th grade.