Ryan Lim Email & Phone Number

Letchworth Garden City, Gb

Letchworth Garden City, Gb

Cambridge

Some key highlights: • Reviewed, and implemented many aspects of the ARC700 core architecture, and system architecture (Memory sub-system, caches, XYmemory...). Key person behind the introduction and implementation of the processor “island” for timing and functional isolation of the core and the system. Also implemented the Instruction caches, debug modules and DSP XY memory extensions and many more.• One of the key Architects behind the ARCVideo platform. Working on many aspects, plus… Show more Some key highlights: • Reviewed, and implemented many aspects of the ARC700 core architecture, and system architecture (Memory sub-system, caches, XYmemory...). Key person behind the introduction and implementation of the processor “island” for timing and functional isolation of the core and the system. Also implemented the Instruction caches, debug modules and DSP XY memory extensions and many more.• One of the key Architects behind the ARCVideo platform. Working on many aspects, plus specialising on the memory sub-system, 2D DMA engines, Motion estimation engines, Entropy Encoder and Decoder extension and engines. Well versed in h.264 and various other Video codec's. Show less

Specified the overall structure of the memory sub-system of a DSP micro-architecture and implement a number of critical sub-modules in the DSP. Lead in a group to implement and partition the memory sub-system. Perform Integration and testing of the memory sub-system modules from a number of designers to form the memory sub-system of a processor. Also worked in a team on the interlocking and RAW hazard handling logic and signalling. Performed floor-planning, place and route. Worked on early… Show more Specified the overall structure of the memory sub-system of a DSP micro-architecture and implement a number of critical sub-modules in the DSP. Lead in a group to implement and partition the memory sub-system. Perform Integration and testing of the memory sub-system modules from a number of designers to form the memory sub-system of a processor. Also worked in a team on the interlocking and RAW hazard handling logic and signalling. Performed floor-planning, place and route. Worked on early specification work on H.264 video decoders. Show less

Liaised with the IP providers to create the appropriate specification of IC modules. Analysis of system architecture using ‘C’ based models. Designed the display unit’s bus interface, arbitration and control unit of a TV controller. Implemented high speed bus bridge. Redesigned major sections of a pixel graphic module. Involved in creating, executing, troubleshooting and maintaining core level VHDL and VERILOG based regression testbenches. Evaluated module functionality and IO timings of ICs on… Show more Liaised with the IP providers to create the appropriate specification of IC modules. Analysis of system architecture using ‘C’ based models. Designed the display unit’s bus interface, arbitration and control unit of a TV controller. Implemented high speed bus bridge. Redesigned major sections of a pixel graphic module. Involved in creating, executing, troubleshooting and maintaining core level VHDL and VERILOG based regression testbenches. Evaluated module functionality and IO timings of ICs on evaluation boards. Liaised with external customers to carry out ‘co-verification’ of ICs. Conducted technical interviews. Show less

Phd, Digital Neuromorphic Systems

• Developed high speed neuromorphic digital hardware modeling the signal processing neural pathways of the human brain. • Implemented.

Beng(Hons), Electronics & Electrical Engineering

Final year project won the ERA Technology Prize for demonstrating the Best Principle of Design. Graduated with 1st Class Honors.