System Verilog based RTL design for the I/O accelerator portion of a RAID on Chip design. I work closely with verification, firmware, emulation, and architecture to define and implement the micro-architectural specification on all next generations ROCs as well as supporting all previous generations.

System Verilog RTL design of the power management unit for Intel's low power SoCs. I worked closely with firmware designers, validation engineers, and SoC customers to design world class power management systems for next generation Intel products.

System Verilog based micro-architecture specification and design for the portion of an ASIC responsible for the power up sequencing, clock gating, and power gating of the phy layer of a high speed serial I/O controller. Worked closely with analog circuit designers to design, integrate and debug behavioral models within the RTL simulation environment. Worked with the validation team to prepare and execute unit level and system level test plans.

Worked as a graduate teaching assistant in both Introduction to Digital Logic and Hardware Organization and Design holding weekly office hours to guide undergraduate students as well as grading homework and exams.