Michael Bergh Email & Phone Number

Boise, Idaho Area

Cupertino, Ca

Mac Pro, Mac Mini, XServe, MacBook AirResponsible for all aspects of developing and delivering an SMC software solution for Mac Pro, Mac Mini, XServe, and MacBook Air projects* Responsible for thermal and power control algorithm implementation and validation for maintaining device temperatures while maximizing user experience by way of fan control and power throttling* Implemented a control loop for a fast-moving temperature which led to a patent filing for Apple* Architected and implemented a thermal control solution for dual GPUs on the new Mac Pro* Cross functional work with Thermal, Physical Design, Platform Architecture, Industrial Design, and EE teams

Cupertino, Ca

MacBook Air and XServeOriginal member of the team who developed the firmware and software for the system controller in the first Intel based Macs* Designed and implemented firmware drivers for the serial interface and PWM* Designed and implemented C software for the ambient light sensor, time-of-day, and serial port applications* Architected and implemented an I2C slave driver within the SMC for network communication with XServe while in power down mode* Worked with ambient light sensor vendors to define and validate more sensitive hardware for the first MacBook Air and developed a C algorithm to calculate higher resolution lux readings

Cupertino, Ca

U2, U3, U3 Twins, Kodiak projects (PowerPC chipsets), and Magma project (Video Execution Unit)* Developed a standalone Vera/Verilog testbench and test suite for the Processor Interconnect Unit* Implemented a chip level at-speed test vector generation flow and Verilog test vector playback testbench* Wrote directed tests to exercise the critical paths in the chip for speed binning and bring-up debug* Utilized CoverMeter to analyze PCI block test coverage then wrote additional directed tests to increase coverage to 95%* Wrote directed tests for the Memory Unit and Load/Store Unit* Traced failing tests to root-cause RTL bugs in the design* Utilized Verplex equivalence checking tool to verify gate level model against verified RTL model

Sunnyvale, Ca

Millennium project (UltraSPARC V)* Led the Integer Unit integration effort including floorplanning, pin placement, routing, RC extraction, and timing analysis* Designed 57 instruction Floating Point Graphics Adder in Verilog* Developed C++ model to simulate performance of various Integer Unit configurations* Developed the initial Integer Unit stand alone test environment

Sunnyvale, Ca

Eagle project (microSPARC IIep)* Designed and implemented regression flow for analyzing the results of RTL and gate level models. The implementation comprised of C Shell, Perl, and TCL/TK scripts as well as a web site for access to results* Traced failing diagnostics to find RTL and gate level bugs* Led a team of four people in verifying a gate level chip model

Master Of Science (M.S.), Electrical Engineering

IC Testing, VLSI Design, Logic Design, Comparative Computer Architecture, High Level Logic Synthesis, Modern Network Analysis, Switching.

Bachelor Of Science (B.S.), Electrical Engineering And Computer Science

Activities and Societies: Amateur Radio ClubComputer Architecture and Engineering, Microelectronic Devices and Circuits