In charge of technical marketing of 28nm/22nm MCU/eflash/emerging memory evaluation at Al and IoT application

Deputy Division Director ( 2016.4~2019.1)• Function as new process & tool evaluation for pilot line setup and yield /reliability improvement• Module Process development of DRAM memory at STI/BWL/BL/SN loopDeputy Division Director/Senior Department Manager (2015.10~2016.3)• Function as Diffusion module related process development• Gox, SiGe, Imp., High-k depo, ALD SP & thermal process developmentSenior Technical Department Manager (2013.6~ 2015.9)• Join IBM 10nm alliance at NY/US (2013.8~2014.4)• Contact window of 10nm & finfet of DF related process development (2014.5~2015.9) Department Manager (2008.4~2013.1)• Function as Diffusion related technical development. New node tool evaluation and Cross-group communication, recruiting, employee training. Senior Section Manager ( 2003.11~2008.4)/ Sr. Development Engineer (2003.5~2003.11) •Function as project leader to develop 65nm/45nm FOEL process. STI liner ox , Gate dielectric/ electrode formation, Spacer film control and wet clean Si recess/ residue related technology

Senior Process Development Engineer (2000.2~2003.3)• 0.13/0.11um Stack DRAM co-develop with Toshiba and Fujitsu at Japan ( 2000.9 ~ 2001.11 ) • 0.18/0.13um ACT1 Flash process evaluation and module integration setupProcess Section Manager (1997.4~2000.1)/ Process engineer (1995.5~1997.3)• Lead diffusion process division for new process pilot run and production• Process optimization and standard operation procedure established

Diffusion module process optimization and yield enhancement.