Michael Ruff Email & Phone Number

Richardson, TX, US

Santa Clara, California, US

My career has come full circle, I'm back to vectors and matrices but this time it's in things you carry vs. racks in a data center. I guess in the end it's all vectors and matrices in this simulation we call life.

Redmond, Washington, US

o Managing a Cloud Hardware Infrastructure Engineering (CHIE) team to develop the FPGA board support RTL and manufacturing test images for an internal, multiple FPGA platform to be deployed in Azure. Responsibilies include direct management, recruiting, requirements alignment between groups, development tooling and automation in addition to significant.

Redmond, Washington, US

Santa Clara, California, US

o RTL design lead for the IPG testchip development team for leading edge process IP. Developed top level clock and reset control logic as well as integration of IP blocks into the test chip. To increase productivity to support multiple test chips per year, I co-architectend and developed tooing which assempled testchips from a spreadsheet specification.

Boise, Idaho, US

o Member of a 3 person team developing an instruction set simulator for a custom processing core written in C++. We provided a fully functional simulator from scratch within 2 months. Specific responsibilities include instruction decoding, instruction performance estimation as well implementing the arithmetic instructions. Interfaced with compiler and.

Richardson, Texas, US

o Participated in the on-site training of customers for the Hybrid-Threading toolset; including presentations, example design development, tool evaluation and relationship building.o Member of development team for the Hybrid-Threading SystemC toolset; responsibilities included co-specification of tool input formats and features; development of the host.

Dallas, TX, US

o A senior member of a physical design team for a 65nm C6X DSP based video coprocessor utilized in OMAP application processors. Supported floor planing, as well as dynamically adjusted power structure and sythesizable register based data path integration. Also participated in specification and received training for Sonics OCP-IP on-chip interconnect.

US

o Began architecting and designing a FPGA (Xilinx Virtexii Pro) which would augment the Lookup and Rate­Meter capabilities of the intel IXP2800 Network processor. The FPGA utilized embedded PowerPC microprocessors, custom state machines and interfaces to QDR SRAM and RLDRAM Il with core frequencies of 100 and 200 MHz.o Developed TCL scripts which configure.

Dorval, Quebec, CA

o Managed ASIC design team: mentoring, task assignment, scheduling, performance evaluation, oncampus recruiting, phone screening, interviewing and hiring decisionso Participated in the specification of a hierarchical COT EDA tool flow for a UMC 150 nm processo Led the design and contributed to the architecture of a deeply pipelined graphics rendering.

Houston, Texas, US

o Verified system performance for V-Class SMP servero Developed enhanced memory interface to improve performance of the V-class server; design responsibilities included majority of the data-path, memory request table and development and execution of ASIC physical design tool flow

o Primary hardware support person for lab integration of the S-class server; debugged hardware andsoftware anomaiies utilizing logic analyzers, scan hardware and intuitiono Developed cross-bar ASIC used in S/X/V-Class servers; 1.1M gate, 0.35 um CMOS gate array, 125MHZ core clock; individually responsible for all aspects of the design process.

o Verified GaAs gate arrays used in PARISC SMP serverso Developed verification tools in C which were integrated into Verilog simulations utilizing PLI interfaceso Participated in the development of an architectural simulator in C++ for a PARISC SMP servero Maintained and enhanced I/O function test suite which inciuded porting to various Unix’s