Michael Ruff Email & Phone Number

Richardson, Tx, Us

Richardson, Tx, Us

Santa Clara, California, Us

My career has come full circle, I'm back to vectors and matrices but this time it's in things you carry vs. racks in a data center. I guess in the end it's all vectors and matrices in this simulation we call life.

Redmond, Washington, Us

o Managing a Cloud Hardware Infrastructure Engineering (CHIE) team to develop the FPGA board support RTL and manufacturing test images for an internal, multiple FPGA platform to be deployed in Azure. Responsibilies include direct management, recruiting, requirements alignment between groups, development tooling and automation in addition to significant individual technical contributions.o Managed the CHIE FPGA Tools team which focused on design environment and tooling in support of FPGA development across all Azure FPGA development groups. Areas of focus include Azure DevOps CI/CD, build pipelines, lab tooling, builds systems and Co-Simulation. Championed metrics-based development as well as simulation verification.o Performed numerous technical evaluations of FPGA IP to offload and accelerate functionality in Azure using the Catapult SW/RTL stack. Primary areas of focus were cryptography and compression. The evaluation included both the FPGA design as well as representative software to fully analyze the end to end solution.o Primary technical resource for evaluation of FPGA offload acceleration in Azure for a custom application of a major Oil and Gas corporation. The responsibilities included architecture, design, implementation evaluation of the design to measure the performance characteristics of the solution for both hardware and software. Presented the results of the evaluation to senior technical management of both the company and Microsoft. As part of the this effort, contributed to the development of the Catapult Co-Simulation environment to enable Hw/Sw codevelopment.

Redmond, Washington, Us

Santa Clara, California, Us

o RTL design lead for the IPG testchip development team for leading edge process IP. Developed top level clock and reset control logic as well as integration of IP blocks into the test chip. To increase productivity to support multiple test chips per year, I co-architectend and developed tooing which assempled testchips from a spreadsheet specification which included fanout waypoint specification for signal propogation across the chip. This tooling was implemented with a collection of Perl, C++ (graph path search) as well as Make and was utilized to assemble multiple test chips.

Boise, Idaho, Us

o Member of a 3 person team developing an instruction set simulator for a custom processing core written in C++. We provided a fully functional simulator from scratch within 2 months. Specific responsibilities include instruction decoding, instruction performance estimation as well implementing the arithmetic instructions. Interfaced with compiler and assembler teams to generate instruction decode source code from tables utilizing Perl.

Richardson, Texas, Us

o Participated in the on-site training of customers for the Hybrid-Threading toolset; including presentations, example design development, tool evaluation and relationship building.o Member of development team for the Hybrid-Threading SystemC toolset; responsibilities included co-specification of tool input formats and features; development of the host interface C++ library and corresponding hardware; Make file tool flow including FPGA implementation; regression testing and triage; identifying suitable C to Verilog mapping constructs as well as primary verification for Verilog mapping issues.o Member of development team for Memcached personality with responsibilities for the packet input processing and results output streaming interfaces as well as the implementation.o Co-developer of Burrows-Wheeler Aligner (BWA) v0.5 personality.o Developed Convey BLAST personality, which required profiling application, investigating academic research, RTL design and implementation. Developed and maintained the relationship between Convey and Boston University lab that provided the basic research for the algorithms utilizedo Designed and implemented many components used in the system infrastructure FPGAs of the Hybrid-Core accelerator including; host caching agent for Intel FSB protocol as well as the instruction cache, branch target/history cache, 32/64-bit scalar and floating-point data path for a custom processor. Also lead the integration and implementation for multiple infrastructure FPGAs. o Developed multiple parameterized RTL building blocks utilized by multiple FPGA designs and designers; including clock crossing synchronizer, FIFO with asynchronous support, virtual queuing and a tree bases N-way round-robin arbiter.o Developed and maintained a batch based FPGA implementation flow for Xilinx ISE targeted FPGAs that was used by multiple internally developed chips. This flow was leveraged and used externally by customers in the personality development kit (PDK).

Dallas, Tx, Us

o A senior member of a physical design team for a 65nm C6X DSP based video coprocessor utilized in OMAP application processors. Supported floor planing, as well as dynamically adjusted power structure and sythesizable register based data path integration. Also participated in specification and received training for Sonics OCP-IP on-chip interconnect generation.o Analyzed feasibility of synthesizing legacy latch based data path for C6X DSP core by patching original RTL sufficiently for Design Compiler to process the sources and generate timing reports.o Analyzed critical timing paths for a DSP cache/memory controller to be implemented in GS60, a 65 nm CMOS process. This included building wire models, representative netlists and timing report spreadsheets.o Maintained and optimized high level floorplan for a block, which utilized a DSP core, caches, local memory and external on-chip, interfaces. This floorplan was used for SPICE net length estimation and block size estimation.o Designed and implemented SRAM memory banks, which contained multiple, distributed multiplexer data paths utilizing a structured logic methodology.o Designed and implemented Perl scripts which generated disk space usage reports for numerous NetApp volumes which were used to identify heavy resource users.

Us

o Began architecting and designing a FPGA (Xilinx Virtexii Pro) which would augment the Lookup and Rate­Meter capabilities of the intel IXP2800 Network processor. The FPGA utilized embedded PowerPC microprocessors, custom state machines and interfaces to QDR SRAM and RLDRAM Il with core frequencies of 100 and 200 MHz.o Developed TCL scripts which configure a Broadcom 12 port Gb Ethernet switch utilizing an I2C interface. Worked to minimize initialization to exceed the boot time requirements while maintaining required functionality.o Participated in the specification and development of FPGAs (Altera Stratix­GX) to encapsulate OIFSPI4-P2 in FEC protected cells across 5 channel-bonded 3.125 Gbps CDR links with core frequencies of 156 MHz.o Designed and implemented interface logic for numerous FPGAs using CDRs, 622 MHZ SDR and 311 MHz DDR source synchronous logic. Developed and implemented a batch oriented flat tool flow for Xilinx Virtexll and Virtexll-Pro devices utilizing Makefìles. Performed FPGA pinout and initial physical implementation for numerous FPGA designs.o Participated in the logical design and hierarchical physical implementation of four gate array ASICs with core frequencies of 156 MHz and 311 MHz. Tasks included floorplanning, synthesis, place and route, timing closure and formal verification. Developed scripts and Makefiles, which facilitated the automation of the hierarchical synthesis and physical design flows.o Led the architecture and implementation of an arbitration concentration ASIC which also provided minimal Ethernet switching. This design utilized an OIF PL3 interface and custom serial CDR links implemented in Fujitsu’s CS81, 180 nm standard cell process with a core frequency of 156 MHz.o Evaluated and qualified tool upgrades for EDA toolsets on Linux, Solaris and Windows. Also performed system administration for Linux and Solaris boxes, which included patch updates, OS installations and configuration.

Dorval, Quebec, Ca

o Managed ASIC design team: mentoring, task assignment, scheduling, performance evaluation, oncampus recruiting, phone screening, interviewing and hiring decisionso Participated in the specification of a hierarchical COT EDA tool flow for a UMC 150 nm processo Led the design and contributed to the architecture of a deeply pipelined graphics rendering engineutiiizing muiti-ported cacheso Specified requirements for third­ party standard cells, IP macros, BGA packages and heat sinks,which required interfacing with representatives from various companies to arrange schedules, deliverables and managing technical tradeoffso Performed electrical analysis for a proprietary source synchronous 64-bit DDR bus interface and 256bit DDR-SDRAM interface; specified and simulated various PCB topologies, SSTL_2 buffer characteristics and package models with HSPlCE to meet the desired eiectrical requirements; developed required skills while performing analysiso Assumed a technical leadership role for the logical design of a proprietary 64-bit DDR buss; optimized bus protocol and control logic to maximize utilization and minimize latency, participated in the architecture of an asynchronous memory interfaceo Integrated and evaluated hybrid COT/ASIC EDA tool flow for the Samsung MDL11O and MDL12Oembedded DRAM process. Led physicai design team utiiizing the flow to implement graphic shaders with embedded DRAM.

Houston, Texas, Us

o Verified system performance for V-Class SMP servero Developed enhanced memory interface to improve performance of the V-class server; design responsibilities included majority of the data-path, memory request table and development and execution of ASIC physical design tool flow

o Primary hardware support person for lab integration of the S-class server; debugged hardware andsoftware anomaiies utilizing logic analyzers, scan hardware and intuitiono Developed cross-bar ASIC used in S/X/V-Class servers; 1.1M gate, 0.35 um CMOS gate array, 125MHZ core clock; individually responsible for all aspects of the design process: specification, Verilog coding, verification, synthesis, place & route, timing and testabilityo Designed JTAG scan interface and clock control logic which was embedded into five ASIC designsused inthe S/X/V-class servers

o Verified GaAs gate arrays used in PARISC SMP serverso Developed verification tools in C which were integrated into Verilog simulations utilizing PLI interfaceso Participated in the development of an architectural simulator in C++ for a PARISC SMP servero Maintained and enhanced I/O function test suite which inciuded porting to various Unix’s