Ming Lee Email & Phone Number

New Taipei City, Taiwan

Hsinchu City, Taiwan, Taiwan

1. Task base analysis:- Bitcell (AC/DC SNM, AC/DC write margin, leakage, Read current...)- SA differential voltage, Effect Write Time (EWT)- Keeper (High Speed 2 Port Register File read port analysis)2. SRAM compiler design:- Characterization flow enable- Measurement/Probe evaluation 3. SRAM circuit design (High Speed 1 Port Register File)(0.18nm) :- Setup/hold time review- Read Write margin tuning- Logic margin tuning- Power Performance Area evaluation - ECOUseful script generating (Python, Cshrc)

台灣 臺北市

• 200+ Top conference, journal paper survey and benchmark• Developed Verilog-A model for advance devices including 2D material FETs, FinFET, Nanosheet.• Various 6T/8T SRAM Layout design• Thermal - Electrical simulation framework for advance FETs SRAM array analysis• Power, Performance, Area and Cost (PPAC) analysis for advance FETs SRAM array• Next generation Design of CFET SRAM

台灣 臺北市

Course: Memory Circuit Technology• Solved and clarified students’ concerns and questions related to the course

台灣 臺北市

Course: From Fundamentals of Semiconductor Devices to Nanometer-Scale CMOS Transistors • Led other three TA and handled the class which near 100 people• Solved students’questions related to the semiconductor physic• Wrote the NTU EE journal which gave profound and detailed introductions of Prof. Yuan Taur

Master'S Degree, Graduate Institute Of Electronic Engineering

Bachelor'S Degree, Electrical And Electronics Engineering