James Moore Email & Phone Number

Austin, Texas Area

Austin, Texas Area

Performed all phases of hardware tool design from concept through delivery to support and enhancements. Created reusable IP and communication interfaces. Influenced debug circuitry for platforms as well as platform documentation. Mentored new team members and other teams on processes and shared IP.• Designed current platform debug tool for processors, chipsets, and GPUs. By incorporating Ethernet, allowed every system-under-test to be instrumented which resulted in faster processor system validation. Design included Xilinx Spartan-3 with MicroBlaze and enclosure. Main interfaces included JTAG, I2C, and SPI. Started learning embedded C++.• Designed LPC Post Code reader and ROM emulator that attaches to above platform debug tool via custom SPI interface. Design included Xilinx Spartan-3AN and enclosure.• Supported and updated previous platform debug tool for processors.• Led “Ethernet Working Group” that created new interface between tools and host software. New interface consisted of custom RPC and high-level API that was much simpler for host software.• Contributed to and reviewed Debug section of platform designs and documentation. Promoted reuse across platforms and documents.• Designed traffic generator for custom high-speed serialized memory interface. Helped architect multi-board, multi-FPGA solution and owned schematics and RTL for back-end memory interface and RTL for high speed deserializers and host communication interface. Design included 2 Xilinx Virtex-5s, 11 Spartan-3s, and numerous custom interfaces.• Transitioned fuse reader project to overseas team. Mentored team on project and general processes.• Mentored 2 different co-ops on designing adapter boards. Taught them schematic entry, layout review, hardware bring up, and business processes.

Austin, Texas Area

Performed all phases of hardware tool design from concept through delivery to support and enhancements.• Designed modular, standalone fuse reader for CPUs that greatly simplified tracking processors in labs. Design included multiple interconnected boards, Xilinx Spartan-3 FPGA, and enclosure. Main interfaces included JTAG and I2C.• Mentored co-op on design of subsequent socket boards for above fuse reader.• Upgraded and supported DDR2 error injector. Enhanced error injector functionality and added JTAG and serial and parallel scan functionality. Error injector functionality allowed more accurate ECC & MCA checking. Parallel scan functionality allowed debug even when serial scan chain was broken. Design included 3 Altera Stratix IIs and 1 Max II in UDIMM form factor. Main interfaces included DDR2, parallel scan, and JTAG.• Designed DDR2 SODIMM to SODIMM + UDIMM adapter utilizing rigid flex PCB. Allowed above mentioned DDR2 error injector and parallel scan tool to be used in SODIMM based systems.• Performed schematic entry for controller board of modular fuse reader / writer used in processor production testing.

Austin, Texas Area

Performed some phases of hardware tool designs and learned processes.• Designed a modular parallel scan tool to allow ATE patterns to be developed on low-cost local hardware reducing non-production use of ATEs and allowing faster pattern development. Design included multiple interconnected boards and Xilinx Spartan-3 FPGA. Main interfaces included JTAG, parallel scan, and I2C.• Assisted with updating reference motherboard to add features for production testing of processors.• Performed signal routing on small PCB with FPGA in order to gain better understanding of layout process.

Austin, Texas Area

Assisted on hardware tool designs.• Designed portions of PCI-X 2.0 stimulator. Schematic work included VFD, Mictors for debug, and more. RTL blocks included IO ring, Mictors, VFD, 7-segment LED multiplexer, and more.

Austin, Texas Area

Assisted on hardware tool designs.• Assisted with design of AGP 3.0 stimulator by writing scripts, reviewing schematics and layout, and reworking FPGA prototype boards.• Designed adapter board to connect processor interposer to JTAG tool.