Handling SOC Synthesis and Constraints Development.

Handling STA,SYNTHESIS

Handling SYNTHESIS and STA.

TIMING CLOSURE FOR IO INTERFACES and CDC.

Phoenix is a Low Power DSP chip which works at 155Mhz. C5525 is a member of TI's C5000 fixed-point DSP product family that is designed for ultra low power applications. Its C55x DSP Subsystem achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation.ResponsibilityComplete Setup for LEC has been done.Done LEC at various stages (RTL vs Prescan Netlist, Pre vs Post Scan Netlist and finally for Post Scan Netlist vs Pd… Show more Phoenix is a Low Power DSP chip which works at 155Mhz. C5525 is a member of TI's C5000 fixed-point DSP product family that is designed for ultra low power applications. Its C55x DSP Subsystem achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation.ResponsibilityComplete Setup for LEC has been done.Done LEC at various stages (RTL vs Prescan Netlist, Pre vs Post Scan Netlist and finally for Post Scan Netlist vs Pd Netlist).Debugged the failing points (Non-Equivalence) and provided feedback to the Design and PD team.Worked in calculating power.Handled Timing closure for few Interfaces.Setup and Hold Violations are fixed and provided the ECO's to the PD team.Helping Post PG Activities such as PRP update etc Show less

Timing is the key to performance in today's designs. Timing has always been a difficult task in a chip design cycle. As day by day technology is shrinking, timing convergence becomes a challenge. Because of high design and manufacturing costs, a small percentage of yield loss can also affect the profit. Process in nanometer technologies is difficult to control. Process variations causes timing variations in manufactured chips, causing failures and chips not meeting the performance guaranteed by… Show more Timing is the key to performance in today's designs. Timing has always been a difficult task in a chip design cycle. As day by day technology is shrinking, timing convergence becomes a challenge. Because of high design and manufacturing costs, a small percentage of yield loss can also affect the profit. Process in nanometer technologies is difficult to control. Process variations causes timing variations in manufactured chips, causing failures and chips not meeting the performance guaranteed by design specifications. Hence knowledge on Timing is required.ResponsibilityLearned the Basic Concepts in Synthesis, STA and Formal Verification.Exposure to the tools such as Design Complier, PrimeTime and Formality.Synthesis of two IPs at netlist level is done.Formal Verification for two netlist is done.Timing closure for two interfaces and provided the fixes to the PD team. Show less