• Verilog, VHDL, & SystemVerilog for RTL design.• SystemVerilog for functional verification.• FPGA design concepts (synthesizing Verilog modules on Basys 3 Artix-7 FPGA board).• FPGA prototyping, partitioning, and advanced debugging.• Software testing and quality assurance.

Project title: Hardware Accelerator of a DNA Sequence Classifier using Hardware - Software Co-design Methodology.My role involves the following:• Dataset pre-processing using NLP algorithms to convert the DNA sequence into numerical feature vector to be able to input them to neural networks.• Building and training a modified version of Lenet-5 neural network to classify the DNA sequences.• Converting the Python model into synthesizable C++ model so that it can be synthesized on an FPGA through high-level synthesis (HLS).• Building an automated environment for the process of dataset pre-processing, Python model training, Python model evaluation, Python model conversion, C++ model evaluation, and comparing the classification results of the two models.