Experience in Mixed-Signal layout design, To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Good experience in critical Analog Layout design of blocks such as at PLL, ADC, DAC, LDO, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below.Good Knowledge on Failure Mechanisms by identifying and solving the issues in the layout like Crosstalk, latch up, IR drop, EMIR, Antenna Effect, Matching techniques, Routing, Shielding...etc.Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Ability to understand design constraints and implement high-quality layouts. Excellent communication responsible for timely execution with high quality of layout design.Process or technology experience: TSMC – 2nm, 3nm, . INTEL- 5nm, 7nm, 10nm.