I am a Design Verification Engineer with extensive experience in verifying the complex RTL design for client-based project. Currently I am working with S T Microelectronics client as a DV Engineer, where I am responsible for run the regression, checks the code coverage & functional coverage reports and write the new test cases to improve the coverage for current client-based project. I am using the Cadence's tools such as V-manager for debugging and Sim-Vision for analyzing the waveforms. Throughout my career, I have gained an expertise knowledge in RTL design process and holistic knowledge of verification of RTL design using UVM. My core skills including RTL code using synthesized constructs of HDL as Verilog, FSM-based designs, HVL as System Verilog, Verification Methodology as UVM, simulation, code coverage, functional coverage, assertion and protocols AMBA APB/ AXI.I have done project on USB 2.0 Transceiver Macrocell Interface (UTMI), Router 1x3, and currently working on client-based project in S T Microelectronics.