Mohammed W Rony, Ph.D. Email & Phone Number

Santa Clara, California, Us

Nashville, Tennessee, Us

NBTI & Total Ionizing Dose (TID) effects in deeply scaled HfO2/SiO2/Si gate stack Ge nanowire devices+Tested NBTI/TID behavior to characterize Ge nanowire devices, used charge separation method to estimate oxide/interface traps, reliability & lifetime. Built radiation & two stage NBTI TCAD models to explain the mechanismSingle-event-induced charge collection in Ge-channel pFinFET and GAA devices+Performed heavy ion and pulsed laser tests to characterize bias dependency of Single-Events-Effects (SEE), developed heavy ion model using Sentaurus Process & device, and calibrated to explain the physics behind charge collectionIonizing-Dose-Aware Behavioral Model of A/D Converters for Sphinx C&DH board used in CubeSats+Designed architectural models of Flash, SAR, Pipeline ADCs, performed TID tests to evaluate the parametric radiation sensitivity of commercial ADC Comparison of Total-Ionizing-Dose Effects in Bulk and SOI FinFETs at 90K and 295K+Solved significant challenges associated with TCAD device simulation at cryogenic temperature, performed proton test to characterize device architecture & temperature dependence of radiation-induced trapped-charges3D Full-Band Monte-Carlo Simulation of Hot-Electron Energy Distributions in Gate-All-Around Si Nanowire+Built 3D Monte-Carlo TCAD model and used Subband-BTE solver to characterize Hot-Electron energy distributionsHigh-field stress induced defects characterization in AlGaN/GaN HEMTs+3D TCAD model is developed considering piezoelectric polarization and donor traps at the interface to characterize stress induced defects

Santa Clara, California, Us

Ionizing-Dose-Aware Behavioral Model of A/D Converters for Sphinx C&DH board used in CubeSats+ Ionizing dose aware architectural models of Flash, SAR, Pipeline ADCs are designed for system (board) level simulation+ Planned and executed TID tests to evaluate the parametric radiation sensitivity of A/D converters used in spaceships+ Models are validated using test results both in standalone mood and temperature control loop system of spacecraft+ Millions of sampled data from Monte Carlo runs are pre-processed, analyzed, and plotted using python and MATLAB

Santa Clara, California, Us

+ Built and ran STA model to check non-unate paths in clock network, unconstrained end points, un-clocked sequential nodes, unconnected power pins, un-annotated nets and dirty pins+ Extracted parasitic and ran STA to check setup, hold, transition violations for reg-to-reg timing analysis & optimization+ Manually fixed violations for timing closure, finally checked DRC and LVS of the design and fixed the DRC violations+ Evaluated PV quality to analyze inter-partition violations, provided timing feedback, and refined partition IO constraints+ Generated clock definition & collateral for Syn/APR (1GHz/2GHz) using Tcl/shell scripting & traced missing definition+ Implemented global clock tree and delivered partition floorplan collateral with global clock tree push-down to enablebetter quality CTS runs+ Built full-chip caliber (DRC) model with partitions waivers, synced up with fron-end to validate UW, GW configurations,debugged and generated missing timing reports before running DRC, debugged and cleaned run time errors,+ Ran several iterations of block level PnR to optimize timing, written scripts to check RTL quality and flop stats toprovide RTL feedback and validate RTL fixes, provided scan-inserted net list to ATPG team+ Explored hierarchical design flow by optimizing at synthesis stage, created floorplan boundaries, define timingconstraints, ran APR, troubleshot on the fly, set/unset required G_variables+ Written shell/Tcl scripts to automate Syn/Place/Route/post-CTS layout QoR analysis in a graphical environment

Beaumont, Tx, Us

• PVT modeling of CMOS to reduce short channel effects (SSLOPE=~68mV/dec, DIBL=8mV/V).• Cell delay optimized with low Subthreshold slope.• Low power ASIC implementation with low leakage cell, MTCMOS, DTCMOS, multi-domain VDD• Dual-gate gate-all-around (GAA) Junctionless Nanowire Transistor (JNT) modeling.• Short Channel Effects (SCE) suppression by novel device architecture.• Mobility degradation analysis due to phonon scattering and surface roughness scattering. • Self-heating and effects of quantum confinement on this nano scale device. • Observing classical and quantum behavior for various boundary conditions.• Process variability analysis using Non-Equilibrium Green's Function (NEGF).• Radiation impact and cross-talk noise reduction by designing dual-channel concept.

Dhaka, Bd

Integration and configuration of transmission,core and radio network.• Excellent client communication skills in terms of both business and technical commutations.• Technical analysis, fault handling and enhancement of voice, data and value added services provided by different vendors.• Solid technical skill & troubleshooting experience in the largest DWDM and SDH Optical Network of Bangladesh (700+ SDH & DWDM mux), SDH/PDH/Hybrid Microwave & IP Networking• Allocate and optimize necessary end-to-end capacity for all types of Trunk E1,SS7, SIGTRAN signaling and BTS as per business forecast.• Soft Rerouting (planning, execution) of traffic on emergency and remote support to network engineers for physical fault handling.• Review RF parameters of cell sites and drive test log analysis• Terminal base fault handling regarding RBS and Radio performance related fault.

My responsibility included teaching, preparing question papers, taking exams and other official duties. Learnt to lead and guide a group of people, delivering thoughts and presentations to audiences

Doctor Of Philosophy - Phd, Electrical Engineering

Master’S Degree, Electrical Engineering

Bachelor’S Degree, Electrical And Electronics Engineering