Pranav Kumar Email & Phone Number

Santa Clara, California, Us

Austin, Tx, Us

Performance Counters Based Software Anomaly Detection: Designed a machine learning based anomaly detector that models microarchitectural attacks as behavioral anomalies in terms of security-critical performance counters. Showed how these detectors can easily break via adversarial examples. Work presented at CFAR (UMich) , Samsung Austin and Western Digital .Hardware-Based Malware Detection: Implemented a mechanism to detect side and covert-channel attacks in the microarchitecture via label propagation and subsequently locally detecting label contention violating a set of predefined rules on L1/LLC/BPred/MemBus and physical memory addresses. Additionally, a global detector reduced false positives.Database of Side-Channel Attacks on gem5: For evaluation of such a hardware mechanism, implemented covert-channel attacks through caches, memory bus, branch predictor and also ported Rowhammer, Spectre attacks to AArch64 on gem5. Implemented two versions: standalone attacks and attacks leaking sensitive information from privacy-critical apps.Contention in Function-as-a-Service (FaaS) Systems: Benchmarked AWS Lambda for various network, OS and compute (INT and FP) latencies and determined on an OpenFaaS-based system locally if contention between lambdas could be a performance bottleneck.

Austin, Tx, Us

TA-ed EE382V, Security at the Hardware Software Interface (Instructor: Dr. Mohit Tiwari).

Cambridge, Cambs, Gb

Proposed two new techniques: Context-Aware Cache Management and Cryptic Cache Architecture (WIP) for defending against same or different-core cache-based timing side channel attacks like Prime-Probe and Flush-Reload. Evaluated trade-offs between cache performance and security.

New York, Ny, Us

Designed an optimal 10GHz RF power amplifier using a Gallium Nitride device model. Also, mentored a junior undergraduate on semiconductor device physics and quasi-ballistic transistor models.

Kanpur, Up, In

Implemented an 8-bit microprocessor and sound monitoring system on FPGA.

New York, Ny, Us

Designed an improved virtual-source based transport model for quasi ballistic transistors, the MIT Virtual Source model 2, in Verilog-A.

Master Of Science - Ms, Electrical And Computer Engineering

Bachelor'S Degree, Electrical Engineering