Giorgos Nikiforos Email & Phone Number

Heraklion, Gr

Crete, Greece

London, United Kingdom

Barcelona Area, Spain

Responsible for architecture and micro-architecture verification of ARMv8 Core clusters. Multi-cluster Validation-Cluster Lead.

Barcelona Area, Spain

Responsible for architecture and micro-architecture verification of Core clusters. Multi-cluster Validation-Cluster Lead.

Barcelona Area, Spain

In particular as a member of a small team I am exposed in the complete (x86) intel Architecture and micro-Architecture and reuse and implement new test cases in order to validate the correctness and the functionality of different levels of hierarchy inside chip. Exposed in new techniques of reaching full Architecture and micro architecture coverage. Root cause of RTL bugs and errors.

Barcelona Area, Spain

In particular as a member of a small group I comprehended the design restrictions and the architecture decisions in order to evolve a core cluster.

Computer Architecture and VLSI Laboratory (CARV) Institute of Computer Science (ICS) Foundation for Research and Technology - Hellas (FORTH) Description: Involved in the ENCORE (ENabling technologies for a programmable many-CORE) EU funded FET integrated project. The ENCORE project objective is to achieve a breakthrough on the usability, reliability, code portability, and performance scalability of multicore architectures. ENCORE focuses on runtime management of parallelism and data locality for future heterogeneous many-core processors.In particular, I worked on the design and implementation of network interfaces for the communication between custom CARV-ICS-FORTH FPGA multi-core designs with ARM quad-core test chips over AMBA AXI protocols (designed and implemented by ARM).

Computer Architecture and VLSI Laboratory (CARV) Institute of Computer Science (ICS) Foundation for Research and Technology - Hellas (FORTH) Description: Involved in the SARC (Scalable Computer Architecture) 4-year EU funded FET integrated project. SARC is concerned with long term research in advanced computer architecture, while FORTH focus is on inter-processor communication and future scalable chip multi-processors with cache-integrated network interfaces. In particular, I worked on the design and FPGA prototyping of a cache with configurable scratchpad regions and integration of cache and an RDMA-capable network interface controller for a multiprocessor system [1], [2]. The design is implemented in synthesizable Verilog (~5K lines), in Xilinx Virtex-5 FPGA using the Microblaze softcore 5-stage pipeline processor using ISE, EDK, Chipscope and Floorplaner from Xilinx. Also, involved on the system integration (~10K Verilog lines), interacting with memory controllers, coherence protocols, buses and crossbar Network-on-Chip.

Computer Architecture and VLSI Laboratory (CARV) Institute of Computer Science (ICS) Foundation for Research and Technology - Hellas (FORTH) Description: (MSc Thesis) Hardware design and Xilinx Virtex-2 FPGA implementation of a cache controller with configurable scratchpad regions as a part of the integrated project Scalable Computer Architecture (SARC).

Description: Hardware design in synthesizable Verilog of efficient Modulo Arithmetic Circuits as part of Archimedes II, EU funded project of Technological Educational Institute of Athens.

Master Of Science, Computer Architecture, 9/10

Areas of specialization: • Microelectronic Systems Architecture • Parallel and Distributed Systems Thesis: “FPGA implementation of a Cache.

Diploma In Computer Engineering And Informatics, Computer Engineering And Informatics Department, 8.1/10

Diploma Thesis: “Modulo Arithmetic Circuits” Supervisor: Prof. Dimitrios Nikolos