Niraj Jani Email & Phone Number

Fremont, Ca, Us

Palo Alto, California, Us

Sunnyvale, Ca, Us

Sunnyvale, Ca, Us

 Full Chip PD Activity in Synopsyso Top level Floor planning, Partitioning, Pin Placement, Reuse Block Planning. o Planning FC routing strategy/topology and routing.o Full chip clock planning for top level mesh and clock stations.o Full Chip buffering, HFN, feed through planning for Full Abutment design. o Power Island creation, Isolation Cell Insertion, Level Shifter Placement and power hooks, Always On HFN buffering, Feedthrough planning across Power Domains.  Block level RTL TO GDSII Skillso Floor-Planning, PnR, CTS, Signoff DRC/LVS/ANT/EM/IR/STA, ECOs etc.o Congestion and Timing Closure of High Speed/Low Power/High Density Designs. o Understanding RTL data flow, Provide RTL Feedback to close timing & congestion. o Experienced un using any Industry standard EDA tool set.  Flow/Methodology developmento FC routing procedures and pin assignment flow.o Double Isolation cell, Level Shifter insertion and PG Hook up for Mobile SOC Top.o Block & FC level IR/EM flow development. o PG Network Creation Flow Development.  Scripting/Codingo TCL, C Shell, AWK, Make, Perl, Verilog, C/C++ Assembly, Entry Level Python

Bangalore, Karnataka, In

 Project #9/10/11: Full Chip Floor-planning Activity (Rev-1 and Rev-2) o Technology: 14nm, Tool: First Encounter, App: Premium Snapdragon SOCo Top Level Floor-plan activities, which include following.o Feed through implementationo Top level Power Island creation, always on buffering, PG customization for FC o Level Shifter and Isolation Cell placement and PG Hookups. o Top level transition fixes for High voltage domain.o Working with designer to do preplacement of standard cells, top Level CLP and LEC cleanup, working in multiple tools like SOC encounter, ICC, Olympus to support across tools ECO management, full chip pre-routes and full chip floor-plan PV activity.o Methodology and Flow developed for some of above tasks were used across all other 14nm top level SOC projects worldwide. Supported the flow for all these projects. o Completed 3 Tape Outs for 3 different version Chip while improving the flow and process to finish all above activities faster.  Project #12: 2 Block Level Designs for Modem Sub systemo Technology: 14nm, Tool: ICC2, App: Premium Snapdragon SOCo Role was to Performa Timing Closure, Congestion Cleanup and signoff including DRC/LVS, CLP, LEC, Top Level Timin ECOs, Functional ECO in metal only etc.  Project #13: Full Abutment method evaluation (14nm)o Gole was to study architecture changes needed to being full abutment style top level implementation. And provide feedback to FE owner.

San Jose, California, Us

ASIC PD Tech Lead I @ eInfoChips Inc. Project #14: 2 Hierarchical Blocks & full chip activity, Top Level Routingo Technology: 28nm, Max Clock: 2 GHz, App: Network Router, Tools: Talus, ICC2o H-Block 1: 7.5M Instances, 10 Sub-blocks, 150 macros.o H-Block 2: 2.3M Instances, 8 Sub-blocks, 100 macros. o Partitioning and Integration flow development in ICC, o Sub-block sizing, shaping, pin assignments, Top level Place and route, timing closure, and congestion solving while giving feedback for RTL changes, constraint improvement etc. and converging the block throughout all netlist drops and finally do the sign off. o Top Level Activity: Partitioning blocks, routing strategy/topology construction and routing. Full Chip buffering and feed through planning. o Mentoring and leading team of 8 engineers to close total 20 Blocks to Netlist to GDSII. Project #15: Sub Chip with 12 Hierarchical Blocks and Topo Technology: UMC 40nm, 36 Clocks, max 266Mhz, App: WCDMA,Tools: EDIo Handled team of 3 Memberso Partitioning design, IO placement for sub- blocks, power pushdown, Interface Constraint Creation, o Place & Route, timing closure, congestion solving, and all sign off closures. Sr. ASIC PD Engineer @ eInfoChips Inc. Project #16: 4 Block Level Designo Technology: 40nm, Clocks: 1.2 GHz, App: Network Switcho Block A: 68 Macros, ~1M Inst (2 Implementation)o Block B: 16 Macros, 1.5M Inst (2 Implementation)o Challenge: Close timing, and congestion for very high utilization block and routing intensive designs. Finally, Signoff Timing Closure, PV/IR/EM/LEC, Func ECOs. Project #17: 2 Blocks o Technology: 40nm, Clock: 1.0 GHz, App: Network Routero Design Size : 16 Macros, 2M Instanceso Tools: Talus, PT/PTSI, Conformal LEC, Apache Red Hawk, Calibero Give the early feed back to top level designer about floor plan size and pin placement. RTL changes, constraint improvement etc. o Converging the block throughout all netlist drops and finally do the sign off.

In

Block level Netlist to GDSII implementation. Floor-planning, Place and route, Signoff. Block timing closure, resolving congestion, giving feed-back to designer about Size/shape/Pin placement etc. Technology: 90nm, 130nmTools: SOC Encounter, PT, conformal LEC, Assura

Master Of Science - M.Sc., Electronics

Bachelor Of Science - B.Sc., Electronics

Education record