Experienced Physical Design and EDA engineer, familiar with all aspects of ASIC implementation, including place and route, physical verification, extraction and CAD infrastructure. Worked on multiple 3D IC tapeouts in technologies ranging from 150nm down to 40nm including planar low power and SOI, responsible for developing tapeout methodologies for the same.Also worked as a part of technology enablement group at GLOBALFOUNDRIES, responsible for design finishing and design for manufacturability CAD flow development for various technology nodes leading up to 7nm.In my current role, I work as Product Engineer in Digital and Sign-off Group at Cadence Design Systems, primarily focused on Innovus & Cerebrus roadmap for leading edge technology nodes.