Worked in the integrated circuits and semiconductor industry designing, maintaining and enhancing CAD tools and infrastructure allowing IP designers to validate and release quality designs.• Designed custom software solutions that complemented current IC design and validation flows and methodologies• Implemented and integrated third party custom software tools and flows into current infrastructure resulting in increased capabilities and functionalities• Debugged various tool flows by working with multiple teams and IP designers • Maintained and enhanced the scripts, tools and flows responsible for IP validation and release methodologies• Worked closely with several teams to adapt, adjust and improve work flows that enhance IP development, quality validation and efficiency• Mentored new employees on design practices and standards, programming languages, industry standard tools and software, and project developmentUse of the following industry EDA software and tools:• Synopsys: IC and Library compiler, Primetime• Mentor Graphics: CalibreDRV• Cadence Virtuoso • Perforce (Revision Control Software)• JIRA bug monitoring and trackingObtained technical knowledge of full ASIC design flow, including the following: • Spice simulation• Static timing analysis• LVS, DRC, ERC, boundary and topological checks• ESD and EMIR solutions• Design for manufacturing (DFM)• Able to interpret and analyze the following design formats: LEF, LIB, NDM, Verilog, OASIS, GDS and CDL