Orestis Mousouros Email & Phone Number

Barcelona, Catalonia, Spain

Iráklion, Crete, Greece

• Evaluation and verification of RDMA Engines that consists of top of the line Congestion Management mechanisms for HPC purposes, included in each node of a mezzanine network, and with the test environment written in C, Bash scripts, and Python. - Learning and using mezzanines of multiple QFDBs. - Automating the process of evaluation. - Analyzing results with plots and fixing or reporting to the seven (7) member-team about any issues.• Further development and evaluation of my master thesis' high-performance Hardware Block, using multiple Trenz for RISC-V cross-coherence-island core communication, with libraries and testbenches written in C. - Solving most common corner cases. - Learning about exception mechanism and interrupt handler.

Iráklion, Crete, Greece

• Designed and developed a high-performance Hardware Block for stream communication, tightly coupled with RISC-V cores, as the master thesis project, part of RED-SEA project, on the subject of “Stream communication in RISC-V cross-Coherence-Islands, with Read-Invalidate and Write-through-Combine Cache Policies”, a new networking framework in a concurrent HPC environment, for the purpose of reducing time needed to fetch and process streams of remote data, with delay similar to the access of a L1 Cache of a RISC-V processor, which is 2 clock cycles for fetched data. - Familiarization with and integration of master thesis project in existing RISV-V architecture (CVA6 CPU, former Ariane, a 6-stage, in-order, 64-bit core). - Upgrading LSU to support communication with both L1 Cache and Stream Cache.• Designed and developed a high-performance Hardware Block for synchronizing nodes of a concurrent network (first version of global clock mechanism), for Congestion Management purposes. - Designing, Debugging and Integration of Hardware IPs/SoCs. - Understanding of more complex Network Protocols, Interconnects, and Scheduling Policies. - Extended knowledge on FPGAs and reconfigurable architectures.• Integration of my bachelor thesis’ high-performance Hardware Block on the ExaNet RDMA send engine, for the purpose of adapting into the project, learning and working cooperatively within the team.

Iráklion, Crete, Greece

• Designed and developed a high-performance Hardware Block for 4-ary priority heap to implement packet-level network rate limiter, as the bachelor thesis project, part of ExaNeSt project (European Exascale System Interconnect and Storage), on the subject of “Heap Implementation in Hardware for Flow Scheduling in a Remote DMA Engine” written in Verilog using Xilinx tools, which can be used to rate-limit flows for congestion management purposes - Hardware RTL design, Implementation, Simulation, Verification

Iráklion, Crete, Greece

• Implementation of CPU thread parallel C++ design with significant speedup, based on existing neuronal analysis written in Matlab, using Spike Time Tiling Coefficient algorithm• Computational Neuroscience and Implementation of neuronal correlations for brain network analysis, in cooperation with Smirnakis Lab at Brigham and Women’s Hospital

Duties: supervising, student counseling, student assesment.Courses:1. HY-120: Digital Design, Fall 2019;2. HY-240: Data Structures, Spring 2020;3. HY-120: Digital Design, Fall 2020;4. HY-534: Packet Switch Architecture, Spring 2021;5. HY-120: Digital Design, Fall 2021.

Master'S Degree, Microarchitecture, Parallel And Distributed Systems, 8.14/10

During my Master's studies, I focused on the field of HW engineering, by designing and implementing a networking framework for stream.

Bachelor'S Degree, Computer Science, 7.71/10