Principal Application Engineer
Current
Sep 2022 - Present
AeroLeads people directory · profile
Pascal Blanc Email & Phone Number
Principal Application Engineer at Cadence Design Systems
at
Cadence Design Systems
1 work email found
@st.com
LinkedIn matched
✓ Verified May 2026
4 data sources
Profile completeness 100%
Current company
Role
Principal Application Engineer at Cadence Design Systems
Location
Grenoble, Auvergne-Rhône-Alpes, France
Company size
Who is Pascal Blanc? Overview
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Quick answer
Pascal Blanc is listed as Principal Application Engineer at Cadence Design Systems at Cadence Design Systems, a company with 10 employees, based in Grenoble, Auvergne-Rhône-Alpes, France. AeroLeads shows a work email signal at st.com and a matched LinkedIn profile for Pascal Blanc.
Pascal Blanc previously worked as Principal Application Engineer at Cadence Design Systems and Digital HW Senior Staff Engineer at Stmicroelectronics. Pascal Blanc holds Engineering, Microelectronics from Institut National Polytechnique De Grenoble.
Company email context
Email format at Cadence Design Systems
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{first}.{last}@st.com
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AeroLeads found 1 current-domain work email signal for Pascal Blanc. Compare company email patterns before reaching out.
Profile bio
About Pascal Blanc
Pascal Blanc is a Principal Application Engineer at Cadence Design Systems at Cadence Design Systems. He possess expertise in dft, low power design, logic synthesis, atpg, upf and 15 more skills.
Listed skills include Dft, Low Power Design, Logic Synthesis, Atpg, and 16 others.
Current workplace
Pascal Blanc's current company
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Cadence Design Systems
7 roles
Pascal Blanc work experience
A career timeline built from the work history available for this profile.
Digital Hw Senior Staff Engineer
SoC digital synthesis and low-power (STM32 MCUs) - Physical RTL synthesis - Formal equivalence checking - SDC constraints development and STA/signoff - Power analysis & optimisation - Implement advanced low-power techniques (power gating, voltage islands, retention, …) - UPF development and power intent verification
Jun 2015 - Sep 2022
Digital Hardware Design Engineer
Digital designer mainly focused on low-power design challenges: - Power intent description (UPF) - Power-aware verification with low-power static checkers and digital simulators - Static and dynamic power analysis
Apr 2013 - May 2015
Digital Hardware Design Engineer
RTL SynthesisUPF development and Low-Power Verification
Jan 2012 - Mar 2013
Feb 2009 - Dec 2011
Aug 2007 - Feb 2009
Trainee
Power consumption estimation and testability improvement of integrated circuits at RTL level
Jan 2007 - Jun 2007
Team & coworkers
Colleagues at Cadence Design Systems
Other employees you can reach at cadence.se. View company contacts for 10 employees →
XX
Xiaoyan Xiong
Colleague at Cadence Design SystemsSan Jose, California, United States, United States
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WP
Wei Pei
Colleague at Cadence Design SystemsChina, China
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AP
Arundhati Porwal
Colleague at Cadence Design SystemsNoida, Uttar Pradesh, India, India
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UM
Uttaradi Mounika
Colleague at Cadence Design SystemsChittoor, Andhra Pradesh, India, India
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JT
Jason Tschopp
Colleague at Cadence Design SystemsRaleigh, North Carolina, United States, United States
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SG
Shyam Ganesh
Colleague at Cadence Design SystemsBengaluru, Karnataka, India, India
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AN
Ankur Narang
Colleague at Cadence Design SystemsNoida, Uttar Pradesh, India, India
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RM
Rod Metcalfe
Colleague at Cadence Design SystemsBracknell, England, United Kingdom, United Kingdom
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SB
Samrudh Bangalore
Colleague at Cadence Design SystemsHamilton, Ontario, Canada, Canada
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MH
Michael Hartman
Colleague at Cadence Design SystemsChandler, Arizona, United States, United States
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Xiaoyan Xiong
Colleague at Cadence Design SystemsSan Jose, California, United States, United States
View →
WP
Wei Pei
Colleague at Cadence Design SystemsChina, China
View →
AP
Arundhati Porwal
Colleague at Cadence Design SystemsNoida, Uttar Pradesh, India, India
View →
UM
Uttaradi Mounika
Colleague at Cadence Design SystemsChittoor, Andhra Pradesh, India, India
View →
JT
Jason Tschopp
Colleague at Cadence Design SystemsRaleigh, North Carolina, United States, United States
View →
SG
Shyam Ganesh
Colleague at Cadence Design SystemsBengaluru, Karnataka, India, India
View →
AN
Ankur Narang
Colleague at Cadence Design SystemsNoida, Uttar Pradesh, India, India
View →
RM
Rod Metcalfe
Colleague at Cadence Design SystemsBracknell, England, United Kingdom, United Kingdom
View →
SB
Samrudh Bangalore
Colleague at Cadence Design SystemsHamilton, Ontario, Canada, Canada
View →
MH
Michael Hartman
Colleague at Cadence Design SystemsChandler, Arizona, United States, United States
View →
1 education record
Pascal Blanc education
FAQ
Frequently asked questions about Pascal Blanc
Quick answers generated from the profile data available on this page.
What company does Pascal Blanc work for?
Pascal Blanc works for Cadence Design Systems.
What is Pascal Blanc's role at Cadence Design Systems?
Pascal Blanc is listed as Principal Application Engineer at Cadence Design Systems at Cadence Design Systems.
What is Pascal Blanc's email address?
AeroLeads has found 1 work email signal at @st.com for Pascal Blanc at Cadence Design Systems.
Where is Pascal Blanc based?
Pascal Blanc is based in Grenoble, Auvergne-Rhône-Alpes, France while working with Cadence Design Systems.
What companies has Pascal Blanc worked for?
Pascal Blanc has worked for Cadence Design Systems, Stmicroelectronics, St-Ericsson, and Defacto Technologies.
Who are Pascal Blanc's colleagues at Cadence Design Systems?
Pascal Blanc's colleagues at Cadence Design Systems include Xiaoyan Xiong, Wei Pei, Arundhati Porwal, Uttaradi Mounika, and Jason Tschopp.
How can I contact Pascal Blanc?
You can use AeroLeads to view verified contact signals for Pascal Blanc at Cadence Design Systems, including work email, phone, and LinkedIn data when available.
What schools did Pascal Blanc attend?
Pascal Blanc holds Engineering, Microelectronics from Institut National Polytechnique De Grenoble.
What skills is Pascal Blanc known for?
Pascal Blanc is listed with skills including Dft, Low Power Design, Logic Synthesis, Atpg, Upf, Digital Ic Design, Scan Insertion, and Soc.
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