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Pascal Blanc Email & Phone Number
Sr Principal Application Engineer
at
Cadence Design Systems
1 work email found
@st.com
LinkedIn matched
✓ Verified Jul 2026
4 data sources
Profile completeness 100%
Current company
Role
Sr Principal Application Engineer
Location
Grenoble, Auvergne-rhône-alpes, France
Company size
Who is Pascal Blanc? Overview
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Quick answer
Pascal Blanc is listed as Sr Principal Application Engineer at Cadence Design Systems, a with 10 employees, based in Grenoble, Auvergne-rhône-alpes, France. AeroLeads shows a work email signal at st.com and a matched LinkedIn profile for Pascal Blanc.
Pascal Blanc previously worked as Sr Principal Application Engineer at Cadence and Principal Application Engineer at Cadence Design Systems. Pascal Blanc holds Engineering, Microelectronics from Institut National Polytechnique De Grenoble.
Company email context
Email format at Cadence Design Systems
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{first}.{last}@st.com
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AeroLeads found 1 current-domain work email signal for Pascal Blanc. Compare company email patterns before reaching out.
Profile bio
About Pascal Blanc
Pascal Blanc is a Sr Principal Application Engineer at Cadence Design Systems. He possess expertise in dft, low power design, logic synthesis, atpg, upf and 15 more skills.
Listed skills include Dft, Low Power Design, Logic Synthesis, Atpg, and 16 others.
Current workplace
Pascal Blanc's current company
Company context helps verify the profile and gives searchers a useful next step.
Cadence Design Systems
8 roles
Pascal Blanc work experience
A career timeline built from the work history available for this profile.
Principal Application Engineer
Digital Hw Senior Staff Engineer
SoC digital synthesis and low-power (STM32 MCUs) - Physical RTL synthesis - Formal equivalence checking - SDC constraints development and STA/signoff - Power analysis & optimisation - Implement advanced low-power techniques (power gating, voltage islands, retention, …) - UPF development and power intent verification
Jun 2015 - Sep 2022
Digital Hardware Design Engineer
Digital designer mainly focused on low-power design challenges : - Power intent description (UPF) - Power-aware verification with low-power static checkers and digital simulators - Static and dynamic power analysis
Apr 2013 - May 2015
Digital Hardware Design Engineer
RTL SynthesisUPF development and Low-Power Verification
Jan 2012 - Mar 2013
Feb 2009 - Dec 2011
Aug 2007 - Feb 2009
Trainee
Power consumption estimation and testability improvement of integrated circuits at RTL level
Jan 2007 - Jun 2007
Team & coworkers
Colleagues at Cadence Design Systems
Other employees you can reach at cadence.se. View company contacts for 10 employees →
VL
Viktor Lapinskii
Colleague at Cadence Design SystemsAustin, Texas, United States
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TK
Tanvir Kazmi
Colleague at Cadence Design SystemsNoida, Uttar Pradesh, India
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RV
Roja Veeramachaneni
Colleague at Cadence Design SystemsUnited States
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JP
Jeannette Padilla
Colleague at Cadence Design SystemsCampbell, California, United States
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KW
Kehan Wang
Colleague at Cadence Design SystemsSan Jose, California, United States
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FC
Frank Creed
Colleague at Cadence Design SystemsWestford, Massachusetts, United States
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DM
Didier Mazzola
Colleague at Cadence Design SystemsSan Jose, California, United States
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DC
Dr. Claudia Roesch
Colleague at Cadence Design SystemsGreater Munich Metropolitan Area, Germany
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AB
Anand Bhujade
Colleague at Cadence Design SystemsNagpur, Maharashtra, India
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GS
G Sravani
Colleague at Cadence Design SystemsMumbai, Maharashtra, India
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Viktor Lapinskii
Colleague at Cadence Design SystemsAustin, Texas, United States
View →
TK
Tanvir Kazmi
Colleague at Cadence Design SystemsNoida, Uttar Pradesh, India
View →
RV
Roja Veeramachaneni
Colleague at Cadence Design SystemsUnited States
View →
JP
Jeannette Padilla
Colleague at Cadence Design SystemsCampbell, California, United States
View →
KW
Kehan Wang
Colleague at Cadence Design SystemsSan Jose, California, United States
View →
FC
Frank Creed
Colleague at Cadence Design SystemsWestford, Massachusetts, United States
View →
DM
Didier Mazzola
Colleague at Cadence Design SystemsSan Jose, California, United States
View →
DC
Dr. Claudia Roesch
Colleague at Cadence Design SystemsGreater Munich Metropolitan Area, Germany
View →
AB
Anand Bhujade
Colleague at Cadence Design SystemsNagpur, Maharashtra, India
View →
GS
G Sravani
Colleague at Cadence Design SystemsMumbai, Maharashtra, India
View →
1 education record
Pascal Blanc education
FAQ
Frequently asked questions about Pascal Blanc
Quick answers generated from the profile data available on this page.
What company does Pascal Blanc work for?
Pascal Blanc works for Cadence Design Systems.
What is Pascal Blanc's role at Cadence Design Systems?
Pascal Blanc is listed as Sr Principal Application Engineer at Cadence Design Systems.
What is Pascal Blanc's email address?
AeroLeads has found 1 work email signal at @st.com for Pascal Blanc at Cadence Design Systems.
Where is Pascal Blanc based?
Pascal Blanc is based in Grenoble, Auvergne-rhône-alpes, France while working with Cadence Design Systems.
What companies has Pascal Blanc worked for?
Pascal Blanc has worked for Cadence, Cadence Design Systems, Stmicroelectronics, St-Ericsson, and Defacto Technologies.
Who are Pascal Blanc's colleagues at Cadence Design Systems?
Pascal Blanc's colleagues at Cadence Design Systems include Viktor Lapinskii, Tanvir Kazmi, Roja Veeramachaneni, Jeannette Padilla, and Kehan Wang.
How can I contact Pascal Blanc?
You can use AeroLeads to view verified contact signals for Pascal Blanc at Cadence Design Systems, including work email, phone, and LinkedIn data when available.
What schools did Pascal Blanc attend?
Pascal Blanc holds Engineering, Microelectronics from Institut National Polytechnique De Grenoble.
What skills is Pascal Blanc known for?
Pascal Blanc is listed with skills including Dft, Low Power Design, Logic Synthesis, Atpg, Upf, Digital Ic Design, Scan Insertion, and Soc.
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