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Pascal Vivet Email & Phone Number

Manager of the 3D Heterogeneous Integration Lab, in the CEA-Leti Silicon Component Division at CEA

Location: Greater Lyon Area, France, France 5 work roles 3 schools

1 work email found @cea.fr LinkedIn matched

✓ Verified Jun 2026 4 data sources Profile completeness 100%

Current company

CEA

Role

Manager of the 3D Heterogeneous Integration Lab, in the CEA-Leti Silicon Component Division

Location

Greater Lyon Area, France, France

Company size

18513 employees

Who is Pascal Vivet? Overview

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Quick answer

Pascal Vivet is listed as Manager of the 3D Heterogeneous Integration Lab, in the CEA-Leti Silicon Component Division at CEA, a company with 18513 employees, based in Greater Lyon Area, France, France. AeroLeads shows a work email signal at cea.fr and a matched LinkedIn profile for Pascal Vivet.

Pascal Vivet previously worked as Scientific Director at Cea and Design & Verification Engineer at Stmicroelectronics. Pascal Vivet holds Doctor Of Philosophy (Phd), Microlectronics, Phd In Microelectronics from Inpg.

Company email context

Email format at CEA

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{first}.{last}@cea.fr

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AeroLeads found 1 current-domain work email signal for Pascal Vivet. Compare company email patterns before reaching out.

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Profile bio

About Pascal Vivet

Pascal Vivet is a Manager of the 3D Heterogeneous Integration Lab, in the CEA-Leti Silicon Component Division at CEA. He possess expertise in nanotechnology, computer architecture, microelectronics, low power architecture, 3d architecture and 3 more skills.

Listed skills include Nanotechnology, Computer Architecture, Microelectronics, Low Power Architecture, and 4 others.

Current workplace

Pascal Vivet's current company

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Cea

Manager of the 3D Heterogeneous Integration Lab, in the CEA-Leti Silicon Component Division

Caluire-et-Cuire, FR

Website

cea.fr

Employees

18513

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Company profile

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5 roles · 23 years

Pascal Vivet work experience

A career timeline built from the work history available for this profile.

Manager Of The 3D Heterogeneous Integration Lab, In The Cea-Leti Silicon Component Division

Cea

Caluire-et-Cuire, FR

Scientific Director

Current

Cea

CEA, Minatec Campus, Grenoble, France

Scientific Director in CEA-Leti, since end 2018.Within the "Architecture, IC Design and Embedded Software" DivisionParticipation to the definition of the main advanced research programs, Responsible of the scientific collaborations,Responsible of the PhD student programs.- Scientific Advisor in the "Digital Circuit and Architecture" Laboratory from 2016 to.

2003 - Present ~23 yrs 5 mos

Design & Verification Engineer

Stmicroelectronics

- Digital Design integration and verification for Video MP4 accelerator engine- Setup of verification methodology (using Specman e-language)- Setup of modelling methodology (using SystemC/TLM)

Jul 2001 - Jun 2003

R&D Innovative Design

Stmicroelectronics

- Setup of asynchronous design methodology (fast simulation, optimized std-cells, pre-synthesis)- Design of a 32-bit asynchronous embedded micro-controller- Evaluation of performances and dissemination

Dec 1999 - Jun 2001

Cad Software Engineer

Anacad Inc. Then Mentor Graphics

Grenoble, France, Then Santa Clara, USA

- CAD software engineer- 6 months in ANACAD Inc. France, on developping Mosfet models within a simulation engine- 16 months in ANACAD Inc. USA., for CAD tool support, spice model development and characterization & fitting

Sep 1994 - Sep 1996

Team & coworkers

Colleagues at CEA

Other employees you can reach at cea.fr. View company contacts for 18513 employees →

CB

Christelle Burle Colleague at CeaSaint-Paul-lez-Durance, Provence-Alpes-Côte d'Azur, France, France View → SC

Sourisseau Christelle Colleague at CeaFrance, France View → RS

Renaud Sirdey Colleague at CeaFrance, France View → PP

Peggy Perroud Colleague at CeaFrance, France View → AM

Aurélie Mazouyès Colleague at CeaFrance, France View → RK

Raef Kamel Colleague at CeaFrance, France View → YM

Yves Minet Colleague at CeaGreater Nimes Area, France View → ST

Sophie Tropini Colleague at CeaÉguilles, Provence-Alpes-Côte d'Azur, France, France View → FD

Frank David-Quillot Colleague at CeaSaint-Pierre-des-Corps, Centre-Val De Loire, France, France View → AC

Arthur Charrue Colleague at CeaTours, Centre-Val De Loire, France, France View →

3 education records

Pascal Vivet education

Doctor Of Philosophy (Phd), Microlectronics, Phd In Microelectronics

Inpg

PhD of INPG university, under the direction of Pr Marc Renaudin, TIMA, PhD work in the France Telecom lab in Meylan, France. - Design of a.

Master, Microelectronics

Université Joseph Fourier (Grenoble I)

Ingénieur (Ex-Telecom Bretagne), Micro-Electronique

Imt Atlantique

FAQ

Frequently asked questions about Pascal Vivet

Quick answers generated from the profile data available on this page.

What company does Pascal Vivet work for?

Pascal Vivet works for CEA.

What is Pascal Vivet's role at CEA?

Pascal Vivet is listed as Manager of the 3D Heterogeneous Integration Lab, in the CEA-Leti Silicon Component Division at CEA.

What is Pascal Vivet's email address?

AeroLeads has found 1 work email signal at @cea.fr for Pascal Vivet at CEA.

Where is Pascal Vivet based?

Pascal Vivet is based in Greater Lyon Area, France, France while working with CEA.

What companies has Pascal Vivet worked for?

Pascal Vivet has worked for Cea, Stmicroelectronics, and Anacad Inc. Then Mentor Graphics.

Who are Pascal Vivet's colleagues at CEA?

Pascal Vivet's colleagues at CEA include Christelle Burle, Sourisseau Christelle, Renaud Sirdey, Peggy Perroud, and Aurélie Mazouyès.

How can I contact Pascal Vivet?

You can use AeroLeads to view verified contact signals for Pascal Vivet at CEA, including work email, phone, and LinkedIn data when available.

What schools did Pascal Vivet attend?

Pascal Vivet holds Doctor Of Philosophy (Phd), Microlectronics, Phd In Microelectronics from Inpg.

What skills is Pascal Vivet known for?

Pascal Vivet is listed with skills including Nanotechnology, Computer Architecture, Microelectronics, Low Power Architecture, 3D Architecture, Asynchronous Design, System Level Architecture, and Systemc Tlm Modelling.

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