Patrick Cheng

Patrick Cheng Email and Phone Number

Senior Member Of Technical Staff Packaging Engineer @ AMD
santa clara, california, united states
Patrick Cheng's Location
Taiwan, Taiwan, Province of China
About Patrick Cheng

 Deliver multiple products with advanced package platforms from path finding development to high volume production including 3DIC (3D V-Cache); 2.5D (CoWoS-S/R/L, EFB (Elevated Fan Out Bridge), Wafer Level Fan-Out (InFO-oS/PoP) and CPI (Chip Package Interaction). 10+ years experienced in project management: design rule extension; technical risk assessment; process flow build-up; trouble shooting; BOM selection; failure analysis, package qualification & mass production. Global Tier 1 subcons management: close collaboration and deep relationships with Fab, OSATs, tool vendors & materials suppliers crossing US, Taiwan, China and Korea. Highly motivated and enthusiasm team player for solving technical issues with fluent bilingualism communication.

Patrick Cheng's Current Company Details
AMD

Amd

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Senior Member Of Technical Staff Packaging Engineer
santa clara, california, united states
Website:
amd.com
Employees:
16705
Patrick Cheng Work Experience Details
  • Amd
    Senior Member Of Technical Staff Packaging Engineer
    Amd Jun 2023 - Present
    Taiwan
    Advanced Technology- Devote to 3DIC (3D V-Cache) new product introduction, pre-ramp up and mass production.- Drive 3DIC (3D V-Cache) technology yields improvement and new factory readiness.
  • Amd
    Member Of Technical Staff Packaging Engineer
    Amd Jun 2021 - Jun 2023
    Taiwan
    Advanced Technology- Develop, qualify and deliver industry's first 3DIC (3D V-Cache) product to the market.- Dedicate to 3DIC (3D V-Cache) process integration, qualification and production.
  • Amd
    Sr. Packaging Engineer
    Amd Aug 2018 - Jun 2021
    Taiwan
    Advanced Technology- Develop, qualify and deliver industry's first EFB (Elevated Fan Out Bridge) product to the market.- Commit packaging process integration & execution for multiple cutting-edge packaging projects including 3DIC, EFB, Wafer Level Fan-Out and advanced wafer node CPI validation.
  • Tsmc
    Engineer
    Tsmc Oct 2014 - Aug 2018
    Taiwan
    New Technology Management (NTM) – Packaging Engineer- Integrated Fan-Out Wafer Level Package (InFO) development. Focus on chip last process flow with heterogeneous integration for application processor of HPC.- Modules-integration: hands-on experience and tooling expertise:- Flip-Chip bonding: fine pitch (<40um) die attach (Shibaura TFC-6000); flux selection (jetting/dipping); reflow profile fine-tune and scaling design.- RDL processing: deliver plating/stripping/etching process BKM for fine width/pitch Cu line (2um/2um) with yield >99.5%.Special Turnkey Program (STP) – Packaging Engineer- N16/N10 advanced IC package development (FCCSP; WLCSP; SiP) for consumer electronics Global Tier1 customer: OSATs management crossing Taiwan, China and Korea.- Deliver ultimate tiny & thin (50um) deep trench IPD package to mass production: bumping; wafer backside grinding; die saw (DRIE; DBG; stealth dicing) and packing (TnR).- Co-develop foremost pick and place tool with 6s inspection & FT electrical tester: tools ability evaluation; visual inspection criteria draw-up and mass production implement.
  • Tsmc
    Intern
    Tsmc May 2013 - Aug 2013
    Taiwan
    - N20 PVD process engineer

Patrick Cheng Education Details

Frequently Asked Questions about Patrick Cheng

What company does Patrick Cheng work for?

Patrick Cheng works for Amd

What is Patrick Cheng's role at the current company?

Patrick Cheng's current role is Senior Member Of Technical Staff Packaging Engineer.

What schools did Patrick Cheng attend?

Patrick Cheng attended Texas A&m University.

Who are Patrick Cheng's colleagues?

Patrick Cheng's colleagues are Shailish Ramautar, Mahesh Inder Singh, Amitabh Das, Phd., Sateesh P, Afeez Adegboyega, Sandeep Raw, Alvaro Razo Medina.

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