Patrick Collier Email & Phone Number

New Jersey, United States

Senior Open Systems Engineer responsible for development of interoperable, evolvable, and sustainable architectures for a variety of applications.

Resident OSA Hardware Subject Matter Expert across Harris Business UnitsAuthored White Paper on the development of Open Product Line ArchitecturesHardware Lead for Vertical Lift Consortium TeamResident Free Space Optics (FSOC)SME

Developed overall technical strategy for SOSA with respect to Multi-C4ISR systemsLead and Chair of the SOSA Hardware Working GroupDeveloped hardware functional decomposition for SOSA hardware systemsDeveloped full set of system level use cases for SOSA Hardware Working Group

HOST Engineering Lead and Hardware Convergence Co-Lead System Designer and EngineerLeading design and development of HOST Embedded Computing Specifications.Developed 3U OpenVPX SBC Slot and Module Profiles for Embedded Computing encompassing a variety of processing architectures.Lead Developer and Chair for VITA 84 HOST Hardware Architecture Team that is designing User Defined Signal I/O standard map to 3U and 6U OpenVPX.Development of high performance computing slices for data analytics, deep learning, and autonomous systems.

Co-founder, Program Manager, and Business Development Manager for the Next Generation Space Interconnect Standard (NGSIS) and co-founder of the Sensor Open System Architecture (SOSA)Founder, current Chair, and Lead for the SpaceVPX and the RapidIO Space Device Class specification effort to develop standard space avionics products.Lead Government and Industry integrated product, specification, policy team.Designed the Performance Diagnostic requirement and algorithm for the RapidIO Space Device Class enhancement for offline Bit Error Rate testing in an operational mode.Designed Payload, Switch, Controller, and Peripheral 6U Slot Profiles for SpaceVPX specification.Lead Core Developer for Sensor Open System Architecture (SOSA) Technical Systems Architecture.Technical Lead and Chair of the SOSA Hardware Working Group.

Space Communications Technical Advisor and Senior Electrical Research Engineer, led critical planning and in-house research and development for team with focus on optics and photonicsLed in-house and contract work on PHY layer optical networking and optical backplanes for laser space communications and intra-satellite communications.SBIR Program Manager for hybrid photonic/mmWave high data rate RF satellite cross-link space communications effort.Developed 4-node 100Gb/s passive optical satellite backplane with RapidIO fabric for data analytics.Designed, developed, and lead team that built and demonstrated a 40Gb/s fiber optic satellite avionics RapidIO/Ethernet network.Designed and developed multi-wavelength 10Gb/s laser communications link using RZ-DPSK, QPSK, and BPPM with simulated fade data through a fast fader.Designed multi-point free space optical network and free space optical small cell architectures.

B.A., Russian

B.A., Physics

M.S., Optical/Electrical Engineering