Patrick Conti Email & Phone Number

Fort Collins, Co, Us

San Diego, Ca, Us

RF/Analog Layout: Chip Lead for the LNA chips we build as Stand Alone solutions or as part of a Qualcomm system solution. In that role, I work with the circuit designers to establish the initial floorplan, put together a schedule, request headcount, lead direct reports onsite and at different geographic locations, coordinate the evolving footprint and circuit trade-offs with the Circuit Design Lead and hold layout reviews at intermediate and final stages.Work for the past 6 years has been the position of Chip Lead. Prior to that, module to block level responsibilities.

San Diego, Ca, Us

Module lead on macro which supplied clocking signals to the rest of the chip. This included laying out multiple blocks and then integrating them with blocks done at another design site. Set up the hundred plus pinout of the Synthesized digital control block to interface properly at the module level. Worked with the Chip Lead to integrate the module and the multiple clock signals at the chip level. Previous work was at block level doing layout of high speed custom digital (Ghz) blocks along with analog layout of highly matched low speed differential circuits such as loop filters.

Spring Hill, Tennessee, Us

Contracted at both Avago in Fort Collins and Qualcomm in San Diego through this excellent contract company which provides Dental, Vision and the ability to purchase group Health. I recommend them to managers and contractors alike for Technical Service recruiting needs.

San Jose, Ca, Us

Analog Layout contributing to a leading edge SERDES tapeout during first assignment. Second, longer assignment was to aid layout teams for SRAM and TCAM memory with IO Bank, BKU, macro builds and digital block builds. Used mainly custom layout but also a small amount of P&R tools when appropriate. Layout being done mostly in the 16ff along with some 28nm CMOS technologies.

San Diego, Ca, Us

Worked in both the mixed signal and RF layout teams. Layout of full custom Analog IP contributing to ADC, Temperature Sensor & Wireless LAN macros on an aggressive tapeout schedule using the current leading edge foundry process. Contract was extended to assist the RF team in their newest nanometer process node also on a very aggressive tapeout schedule. Contract extended for several months to assist in the RF group after working with the Analog & Mixed Signal team. Received good feedback from Circuit design Engineers and peer Mask Designers.

San Jose, Ca, Us

Memory Layout in 28nm CMOS PDK. SRAM layout from leaf cell through full SRAM build. Blocks built include: Decoders, Row Drivers, IO Drivers, Sense Amp Drivers, IO, multiple control macros and Phase Delay blocks. Worked with Design Engineers to improve size, speed and parasitic aspects of physical layout. Worked with Compiler writers to optimize blocks for automatic build of any size sram once a hand built template had been established. Pushed implementation of layout queue software to priortize and track layout requests from Design, Simulation and Automation Engineers. Learned to use a proprietary layout tool and developed basic ability to write functions to speed layout within that tool.

Santa Clara, California, Us

Contract position at the Mile High Design Center- Using Cadence 6.1.x and Mentor Calibre tools to perform leaf cell through block level layout for memory layout team, standard cell library team and for an Analog block team. Worked with Designers in Colorado, Boston and Austin.

Scottsdale, Arizona, Us

Contributed Analog layout of new and existing blocks (re-spins) to three chip tapeouts during this short term contract. Two of those chips taped out during the approximately three months and the third was due to tape out soon thereafter. Layout was done in a 5v-14v process which included BiPolar, High Voltage CMOS, DMOS and standard CMOS transistors. Used Cadence 6.1/VXL with Calibre verification. Learned new skills regarding High Voltage Isolation while in this position, picked up some VCR Auto-Routing skills (custom digital) and managed to impart a small amount of knowledge to the local team regarding the use of Cadence 6.1 features. Was informed by the hiring manager that he was happy with the work done during this short contract.

San Diego, Ca, Us

Analog Layout using one of the earliest 28nm analog design kits while working with an experienced team in the embedded analog group. Worked on two separate projects for an advanced technology tapeout under very aggressive schedules. My tasks included a moderately complex bias macro for a high speed, highly matched two channel device along with second assignment working on routing/connecting macros below the full chip level. Had to come up to speed quickly in a new (to the industry) tool set and technology. Lastly, suggested improvements for pcells and tool functionality to the CAD organization including putting together a test case for verification team.

Analog Mask Designer, Layout of full custom Analog chips. Cell level Layout through full chip and tapeout. Promoted to highest level of non-exempt Mask Designer at National Semiconductor. Sole Layout Designer on several chips at National Semiconductor. Experienced user of Cadence Virtuoso/VXL layout editor. Skilled in DRC/LVS/ERC verification using Assura and Hercules with past experience using Mentor Calibre tools. Experienced in layout techniques to deal with high speed operation, device matching, and capacitive coupling. Familiar with ESD and Latchup protection in regards to layout. Developed outline of content for the layout team populating an internal layout website. Developed, communicated and promoted 'Design to Layout' checklist and ' Post Layout Review' checklist, both of which improved communication between Design Engineering and Layout.

Santa Clara, Ca, Us

Mask Design performed to build 0.13um full custom CMOS Analog and Digital cells. Designs built ranged from logic gates to I/O macros. Designs were built in separate design kits for both TSMC and UMC foundries. A highlight of this work was a full custom sixteen phase clock distribution cell with less than 10ps of margin per phase. This work contributed to the worlds first working 3.125Gbps mixed-signal CMOS part. Also created test layouts for DRC deck validation. Worked with design groups in California and Massachusetts to accomplish company goals. Left company due to Design Center being closed.

San Jose, Ca, Us

Mask Design performed to build 0.18 and 0.13um analog cells per Engineering schematics. Built and modified I/O cells to Engineering schematics. Performed LVS and DRC on analog layouts. Performed schematic driven layout. Trained group of 12 mask designers in I/O layout techniques. Layout performed using Mentor IC STATION. Verification performed using Mentor Calibre. Worked with design and library groups in Minnesota, California and Massachusetts to accomplish company goals.

San Jose, Ca, Us

Performed wafer level failure analysis for LSI-owned wafer fab. This was done using mechanical and chemical deprocessing techniques including lapping, polishing, acid bath and plasma etch. Performed investigative analysis such as micro-probe on failing structures, photo-emission microscopy, Scanning Electron Microscope (SEM) analysis, Focused Ion Beam (FIB) analysis and Electron Beam (E-beam) analysis using integrated tester. Attended national Failure Analysis conference and reported on areas of interest to group.