VLSI Physical Design Engineer• Enthusiastic Electronics Engineering Graduate with VLSI Training. Eager to apply my skills in VLSI methodologies and design flows to contribute meaningfully to the semiconductor industry. As a trainee, has an interest in learning and exploring new ideas and technology.•Here is my skill set:->Digital Electronics: Boolean algebra, Combinational Circuits, Sequential Circuits, FSM, Memories.->HDL Verilog: basic fundamental structural.->CMOS: CMOS fundamentals, CMOS design, layout, and stick Diagrams.-> Physical design: ASIC Flow from RTL to GDS II, Logic Synthesis, Floor planning, Placement, Routing, Clock Tree Synthesis, Static Timing Analysis, DRC, ERC, LVS, and signoff using Caliber.->STA: STA Basics, Comparison with DTA, Timing Path and Constraints, Different types of clocks, Clock domain and Variations, Clock Distribution Networks.->DFT: Basic Fundamentals, MBIST, DRC, Boundary Scan, Scan Chain, IJTAG.•My technical toolkit includes proficiency in Industry-standard tools, and hands-on experiences with:-Creating a project that involves the implementation of synthesis and PNR flow (RTL to GDS II) using RISC-V IP and Router, through DC and ICC2.-Designed and optimized a Pulse Generator for an EDM drill machine-Developed a health monitoring system for coma patients, showcasing the patient's activities on an LCD and notifying doctors and caregivers.•Behavioral Skills:-collaborative-organized-motivated