I lead the packaging solution path-finding, packaging solution development, and reliability management for advanced ASICs and system solutions. Through collaboration with design teams, component suppliers, and foundry / OSAT partners, we have developed and deployed multiple generations of industry-leading large and complex devices. My team and I also support quality issue resolution and reliability improvement for a broad range of component families by utilizing our technical know-how and capabilities such as numerical simulation. My general expertise covers the following:• Extensive experiences in packaging solution development, reliability assessment / improvement, and quality issue resolution for a wide range of IC components and packages• Device families include ASICs in advanced silicon nodes, 3D / 2.5D packages, memories (DRAM, SRAM, Flash), and standard / analog product families; Package families include large-body flip chip BGAs, wire-bond BGAs, and leadframe packages• In-depth knowledge of manufacturing processes for the entire manufacturing chain, from wafer processes, component assembly, to PCB-level assembly• Proven leadership skills in defining, managing, and delivering results for complex technological and business projects that involve global cross-functional teams including manufacturing, development, and business organizations• Active and expansive industry leadership and impact through collaborations with customers, suppliers, contract manufacturers, academia, and industry consortia including IEEE, JEDEC and iNEMI; General chair and technical program chair for multiple IEEE conferences• More than 80 journal and conference publications covering a broad range of topics on IC reliability, manufacturing processes, and material sciences