Pete Manos Email & Phone Number

Eden Prairie, Mn, Us

Semiconductor Technologist and Project Manager, working with current and prospective customers to deliver process technologies to fit their product requirements. Currently driving CAD/EDA requirements to develop robust PDK's for customers to manufacture products on SkyWater's sillcon-based technology nodes.

Taking a lifetime of semiconductor technology experience on the road! Currently assisting client companies with technology development and project management. I can bring insight into silicon design and process, whether you're a large IDM or a small fabless startup.

Bloomington, Mn, Us

Led a great team of engineers and technicians in developing robust devices. Developed LOCOS-based BCD technologies (bipolar, CMOS and DMOS devices) to be operated in the multi-100 volt regime. Successfully prototyped first fully-integrated 180nm STI/DTI technology within company, for use up to 100V operating voltage. TCAD development to minimize silicon Cycles of Learning. Managed cross-functional teams related to PCM, design rule and E=M methodologies.

Fremont, Ca, Us

Development of ST-RAM and ReRAM technologies for use in solid-state disk drives (SSD's). My position was primarily involved as a design liaison to develop design rules, e-test and process monitors for the new technologies. I was also the Technical Lead on a vertical transistor project designed to be used as the access FET for the SSD memories.

Us

Development of optical MEMS technology for use by direct writing systems. Acted as "CMOS expert" in a group of "MEMS experts". Project Manager for foundry transfer.

San Jose, Ca, Us

Technical Lead on multiple development projects: 90nm CMOS, 180nm CMOS, 0.24um SiGe BiCMOS. Technical liaison between technology and design departments, enabling platform development.Development of "etest=models" or "E=M" methodology to align etest requirements with SPICE models, enabling robust designs.

Milpitas, California, Us

Development of device models, design rules, e-test structures and methods. ESD and latchup protection designs for the entire company's product portfolio Extensive involvement in competitive analysis and process development. I managed a group of engineers and technicians, personally spending about 75% in management and 25% doing individual engineering work.

Boise, Idaho, Us

Primarily involved in development of double-poly floating-gate NOR flash technologies at 0.8 and 0.6 um technology nodes. This work encompassed both process integration and device modeling. I was heavily involved with design rule validation and various process and product reliability issues.

Milpitas, California, Us

Responsible for technology development and integration of CMOS technologies at the 1.2um and 0.8um levels. Development of business plans and management of resources and materials for same. Managed direct staff of 6 and dotted-line staff of 8.

Farmington, Ct, Us

Development of CMOS gate array technologies for use in military and aerospace applications, at the 1.0um technology node.

Austin, Texas, Us

Section Manager for ASIC and mixed-signal technology development. Reponsible for technology implementation at the 1.5um level (mixed-signal) and the 1.0um level (ASIC gate arrays)

Santa Clara, California, Us

Involved in EPROM technology development for the NVM product line, using FG technology. Worked as a technical contributor at the 3.0um, 2.0um and 1.5um technology nodes.

M. Eng, Engineering Physics

Non-Degree Classes, Electrical Engineering

Bachelor’S Degree, Physics