Please complete the CAPTCHA to continue
@cadence.com
✓
1 phone found area 603
✓
LinkedIn matched
A concise factual answer block for searchers comparing this professional profile.
Peter Arnoldy is listed as Senior Technical Leader - Application Engineering at Cadence Design Systems, a with 10 employees, based in Nashua, New Hampshire, United States. AeroLeads shows a work email signal at cadence.com, phone signal with area code 603, and a matched LinkedIn profile for Peter Arnoldy.
Peter Arnoldy previously worked as Senior Application Engineer/Systems Engineer at Denali Software and Senior Design Engineer at C-Port Division Of Motorolla. Peter Arnoldy holds Ms Ee, Semiconductor Engineering from Northeastern University.
This section adds company-level context without repeating Peter Arnoldy's masked contact details.
AeroLeads found 1 current-domain work email signal for Peter Arnoldy. Compare company email patterns before reaching out.
Leader responsible for building ASIC design teams and establishing remote design centers for semiconductor companies.Successful marketing engineer with experience giving presentations at conventions and tradeshows, collecting market feedback for Engineering and writing specifications in a systems engineering capacity.Over 20 years in the industry designing semiconductor solutions in the telecom/datacom, video, processor, and defense markets.Specialties: Excellent verbal and writing skills coupled with my extensive technical expertise.
Listed skills include Asic, Pcie, Semiconductors, Ic, and 19 others.
Company context helps verify the profile and gives searchers a useful next step.
A career timeline built from the work history available for this profile.
Digital IP Cores: product definition, system engineering, training, working with customers to write specifications for DDR subsystem, Flash subsystem, PCI-Express subsystem.
Digital IP Cores: product definition, system engineering, training, working with customers to write specifications for DDR subsystem, Flash subsystem, PCI-Express subsystem, Verification IP. Chaired Compliance Work Group of Advanced Switching Interconnect standard committee. Participated in RapidIO standards committee, helped to write and edit the Flow Control specification.
Established the timing methodology for large network processor chip (C5) for use with synthesis and STA scripts. Wrote perl scripts and other code to extract and apply SDC and other design information for use in custom timing flow. Also did System Engineering for processor communications port (PCIe and RapidIO). Wrote proposals for variety of design implementations for communications port. Participated in RapidIO standards committee, helped to write and edit the Flow Control specification.
Established Boston Design Center. Hired ASIC design team. Managed development of several large communications chips.
Put in place the infrastructure to design and build ASICs (selected hardware and CAE tools, wrote style guides, recruited ASIC design team, arranged training for the team, etc).
Developed video communications chip as part of a team of designers. Managed SCSI port development.
Led the effort to bring micro-FLIR motor control, data capture, and pixel processing circuitry into an ASIC. Supervised lab resources and contract resource to insure completion of design phase, lab testing, and on-site integration effort at the end customer.
Designed test equipment.
Other employees you can reach at cadence.se. View company contacts for 10 employees →
Saurabh Varshney
Colleague at Cadence Design SystemsNoida, Uttar Pradesh, India
View →
DR
Dinesh Reddy Vantari
Colleague at Cadence Design SystemsHyderabad, Telangana, India
View →
MC
Ming-Yen Chen
Colleague at Cadence Design SystemsChanghua County, Taiwan, Province Of China
View →
FK
Filzer Kummudiyil
Colleague at Cadence Design SystemsBengaluru, Karnataka, India
View →
LL
Luke Lin
Colleague at Cadence Design SystemsSan Jose, California, United States
View →
LL
Leslie Liu
Colleague at Cadence Design SystemsHsinchu City, Taiwan, Province Of China
View →
TP
Trang Phạm Thị
Colleague at Cadence Design SystemsHanoi, Vietnam, Viet Nam
View →
SS
Sentry Shieh
Colleague at Cadence Design SystemsTaiwan, Province Of China
View →
DV
Devang Vekariya
Colleague at Cadence Design SystemsPune, Maharashtra, India
View →
KP
Kaushik Purushotham
Colleague at Cadence Design SystemsBengaluru, Karnataka, India
View →
Activities and Societies: Tau Beta Pi National Engineering Honors Society
Quick answers generated from the profile data available on this page.
Peter Arnoldy works for Cadence Design Systems.
Peter Arnoldy is listed as Senior Technical Leader - Application Engineering at Cadence Design Systems.
AeroLeads has found 1 work email signal at @cadence.com for Peter Arnoldy at Cadence Design Systems.
AeroLeads has found 1 phone signal(s) with area code 603 for Peter Arnoldy at Cadence Design Systems.
Peter Arnoldy is based in Nashua, New Hampshire, United States while working with Cadence Design Systems.
Peter Arnoldy has worked for Cadence Design Systems, Denali Software, C-Port Division Of Motorolla, Transwitch, and Aware.
Peter Arnoldy's colleagues at Cadence Design Systems include Saurabh Varshney, Dinesh Reddy Vantari, Ming-Yen Chen, Filzer Kummudiyil, and Luke Lin.
You can use AeroLeads to view verified contact signals for Peter Arnoldy at Cadence Design Systems, including work email, phone, and LinkedIn data when available.
Peter Arnoldy holds Ms Ee, Semiconductor Engineering from Northeastern University.
Peter Arnoldy is listed with skills including Asic, Pcie, Semiconductors, Ic, Soc, Mixed Signal, Functional Verification, and Verilog.
Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.
Start free trial Search contactsCheck these profiles if this is not the Peter Arnoldy you were looking for.
