Phil Cayton

Phil Cayton Email and Phone Number

Principal Engineer at Intel Corporation @ Intel Corporation
santa clara, california, united states
Phil Cayton's Location
Portland, Oregon, United States, United States
Phil Cayton's Contact Details

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About Phil Cayton

Phil Cayton is a Principal Engineer at Intel, where he leads research and development in Composable Disaggregated Infrastructures (CDI), HPC fabrics, and local and remote storage. He has over 25 years’ experience in architecture and software design, holds 21+ patents, has 9+ published technical articles, and has presented at many, many conferences.Phil currently serves as Co-Chair of the NVMe Consortium Boot Task Group, Vice Chair of the OpenFabrics Alliance (OFA), Co-Chair of the Ultra Ethernet Consortium (UEC) Storage Work Group, Director on the Board of the OFA representing Intel, and OFA Marketing Working Group Co-Chair. He coordinates and has served as Master of Ceremonies for the annual OFA Workshop for the last 3+ years. He coordinates and sets the agenda for the NVMe Technical Working Group (frequently serving as NVMe TWG Chair). In addition, he serves as a liaison in roles between the OFA, SNIA, DMTF, CXL, and UEC, and is often requested to author and negotiate agreements between industry associations and serve on Technical Program Committees for industry conferences.He is involved with, has worked on, and has influenced several industry standards, including the NVMe specifications, SNIA Swordfish, and the OFA Sunfish CDI framework: He was one of the original architects and designers of NVMe-over-Fabrics, wrote the original NVMe-oF driver stack and NVMe/RDMA transport, is a principal author of the NVMe Boot spec, and helped architect the open-source prototype of booting over NVMe/TCP.He is a lead architect of Sunfish, developing an open-ecosystem technology & vendor agnostic framework for true composable disaggregated server infrastructure using technology agnostic hardware agents.He is a lead architect developing the SNIA Swordfish Storage Management specification and associated profiles and prototypes.Phil's current technical interests include HPC ecosystem, orchestration, and infrastructure including NVM manageability, remote memory, and composable open fabric management framework projects to enable hardware agnostic scalable manageability and composability of disaggregated datacenter infrastructures.He has been involved in InfiniBand at, and since, its inception and led Xeon-PHI and open fabric enterprise network stack development, dynamic data center energy efficiency R&D, server autonomics R&D, HPC composable infrastructure R&D, mobile-device multi-radio interference mitigation projects, mobile augmented reality, sensor-enhanced personal medical monitoring projects, and network driver development activities.

Phil Cayton's Current Company Details
Intel Corporation

Intel Corporation

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Principal Engineer at Intel Corporation
santa clara, california, united states
Website:
intel.com
Employees:
133841
Phil Cayton Work Experience Details
  • Intel Corporation
    Principal Engineer
    Intel Corporation Feb 2024 - Present
    Actively involved in open-ecosystem development of architecture and standards for scalable storage, scalable storage management, HPC/AI fabric interfaces, and composable disaggregated infrastructures to facilitate fabric-agnostic scalable manageability in dynamic heterogeneous infrastructures.
  • Intel Corporation
    Senior Staff Engineer
    Intel Corporation Jan 2017 - Feb 2024
    Architect/developer Open Fabrics Alliance (OFA) Sunfish project developing a scalable Composable disaggregated Infrastructure (CDI) framework for systems composition & management in dynamic heterogeneous datacenter/HPC/AI infrastructures. Goal: connect container engines & workloads with distributed computing resources to maximize workload efficiency & minimize resource isolation and energy waste of idling devices.Co-chair of the NVMe Boot workgroup developing standards to boot via NVMe to enhance composable system & IPU functionality and flexibility. Serves as NVMe Technical Work Group coordinator.SNIA Swordfish specification development and mapping between Swordfish and local and remote NVMe resources to provide a unified approach for management of enterprise storage and servers in hyper-scale & cloud infrastructure environments to enable integrating datacenter scalable solutions.Vice-Chair of the Open Fabrics Alliance, Co-chair of the OFA Marketing Workgroup, Director on the OFA Board.Fosters product scalability & interoperabilitySteered the industry towards award-winning standards based remote storage. Influenced NVMe to drive increased scalability/manageability and drove NVM at scale. Developed an open-source scalable storage automated centralized manageability suite.
  • Intel Corporation
    Staff Engineer
    Intel Corporation Jan 2012 - Jan 2017
    Developer of NVMe-oF, providing modular, fabric-agnostic, high-speed, low-latency, scalable remote access to PCIe attached Nonvolatile Memory (NVM). Developed/Prototyped first NVMe/RDMA Transport. Authored standards proposals, developed & demonstrated 1st NVMe-oF driver prototypes, and led team to develop/deliver NVMe-oF drivers, fabric agnostic interface libraries, and fabric transports.Developed processor capability to provide low-latency user/kernel client access to RDMA via Open Fabrics Enterprise Distribution (OFED) PCIe transactions. Architected/developed kernel-mode verbs into base drivers, designed/developed proxied Connection Manager and Subnet Administrator Clients, developed kernel-mode test modules enabling IPoIB upper-layer protocol. Wrote and submitted patches upstream.
  • Intel Corporation
    Senior Engineer
    Intel Corporation Jan 2004 - Jan 2012
    Researched remote shared NVM (distributed filesystems, transports, schedulers). Designed flow-control & buffer-management. Developed business case, proposals, prototypes.Developed comprehensive end-to-end video and mobile augmented reality suite demonstrating multiple image & frame recognition / feature tracking / edge-detection algorithms.Researcher on a project for reconfigurable architectures to optimize power & die area by reducing gate counts and developing multi-use IP blocks, optimizing performance & power. Researched workloads to identify key hot-spot blocks and bandwidth requirements to optimize for hardware incorporation.Lead team designing sensor enabled mobile health devices for stroke & heart-attack detection, diabetes management, and Emergency Medical Services field usage. Developed embedded software and devices.Engineer on wireless LAN clock control, radio frequency interference mitigation, open & closed loop adaptive clocking projects to reduce multi-radio system RFI (WIFI, WIMAX, WCDMA), obtained 2X performance gains via RFI monitoring & frequency shifting. Wrote GUI, clock-control software, drivers.Developed autonomic cluster & rack managers, sensor feedback & policy engine tools interfacing with ACPI/IPMI, embedded, and wireless sensors for power & cooling efficiency. Improved datacenter energy & thermal efficiency via dynamic plant design & predictive load sharing. Developed network and I/O performance acceleration stacks.
  • Intel Corporation
    Senior Technical Marketing Engineer
    Intel Corporation Jan 2002 - Jan 2004
    Single point of contact for 6 companies for product design/development support.Owned technical support (driver design, benchmarking, investigations of customer reported issues). Led customer coordination to optimize features, delivery, and understand new product requirements.
  • Intel Corporation
    Senior Software Engineer
    Intel Corporation Jan 1999 - Jan 2002
    Designed & developed fabric transport protocol, and driver stacks.Technical Liaison to companies for protocol design, integration, debugging and licensing.
  • Intel Corporation
    Software Engineer
    Intel Corporation Jun 1995 - Jan 1999
    Developed Ethernet adapter drivers.Led performance and interoperability analysis. Owned defect lists, communicated analysis results to customers, wrote design documents, life cycle plans.
  • Openfabrics Alliance
    Board Member
    Openfabrics Alliance Jun 2021 - Present
  • Openfabrics Alliance
    Vice Chair
    Openfabrics Alliance Jun 2020 - Present
  • People'S Electronic Access To Knowledge
    Systems Administrator
    People'S Electronic Access To Knowledge Sep 1992 - Jun 1995
    Non-profit internet service provider.

Phil Cayton Skills

System Architecture Device Drivers Operating Systems Computer Architecture Algorithms Software Development Distributed Systems Linux Linux Kernel High Performance Computing Perl Intel C Computer Science Embedded Systems Debugging Microprocessors File Systems Scalability Storage Software Design Cloud Computing Kernel R&d Wireless Sensor Networks Software Engineering Computer Engineering Architecture Rdma Infiniband

Phil Cayton Education Details

Frequently Asked Questions about Phil Cayton

What company does Phil Cayton work for?

Phil Cayton works for Intel Corporation

What is Phil Cayton's role at the current company?

Phil Cayton's current role is Principal Engineer at Intel Corporation.

What is Phil Cayton's email address?

Phil Cayton's email address is ca****@****ail.com

What schools did Phil Cayton attend?

Phil Cayton attended Oregon Health & Science University, Oregon State University.

What skills is Phil Cayton known for?

Phil Cayton has skills like System Architecture, Device Drivers, Operating Systems, Computer Architecture, Algorithms, Software Development, Distributed Systems, Linux, Linux Kernel, High Performance Computing, Perl, Intel.

Who are Phil Cayton's colleagues?

Phil Cayton's colleagues are Rujuta Panvalkar, Arun Kumar Rana, Ian Bertmaring, Cpe, Hector Vivanco, Jonathan Carson, Manjunath Kamath, Steven Clark.

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