Philip Choi Email & Phone Number

Austin, Texas, United States

Irvine, California, United States

Interface between semiconductor manufacturing foundries and BU engineering teams.Manage Quality Continuous Improvement activities across the Product Development Cycle.

Austin, Texas Area

Product Engineer for the Foundry Service Operations division of NXP Semiconductor responsible for manufacturability and yield enhancement of external MEMs bolometer customer.• Created production control plan linking foundry customer specification with internal fab process capabilities allowing for qualification of the technology• Increased product yield through test structure design, critical process tool improvement and design rule changes• Work closely with foundry services, device, process, test, failure-analysis, reliability and the customer to resolve issues through electrical and physical data characterization, mining and analysis.

Austin, Texas Area

90nm smart power• Led highly visible cross-functional 8D team to address top priority silicon processing issue, utilizing the fishbone root-cause analysis technique. Role included: identification of analysis techniques, determining experiments, coordinating logistics of running silicon and analysis/test across multiple facilities while providing regular updates to stakeholders.• Drove manufacturability and characterization of the technology through collaborative relationship with process, device, test and FA groups. Resolved BEOL issues and HV isolation and breakdown electrical testing.

Austin, Tx

90nm thin film, 90nm split-gate, 55nm automotive• Principal device owner on internal and foundry-based technology developments• Designed and executed device and integration experiments to bring devices to target and keep technology maturity on schedule.

Austin, Texas Area

55nm automotive• Led successful multi-company cross-function team to develop and qualify a high-performance embedded Flash technology in a leading foundry, maturing it from process freeze to production in a timely manner. Requirements ranging from manufacturing marginality and device targeting to NVM reliability and product life-stresses. • Identified bottlenecks in schedule, lack of resources and brokered compromises. Coordinated silicon processing, assembly and testing logistics. • Adapted quickly to constantly changing circumstances. Regularly updated stakeholders on project progress and project teams on stakeholders’ feedback.

• Maintained 130~40nm technology development on schedule, resolved manufacturing issues and supported internal foundry services (capacitor-less SRAM) through improved targeting, reduced variability and more robust reliability (HCI, SEL, SEU) for both front-end and back-end process and devices• Propelled the introduction of a low-energy SIMS tool into the internal analysis lab to more accurately characterize shallow-junctions• Drove TCAD capability as the primary interface with vendor who set priorities and ensured resolution of bugs and enhancement requests• Mentored University of Florida and Los-Alamos National Lab simulation/modeling projects

Doctor Of Philosophy - Phd, Electrical And Electronics Engineering

Master Of Engineering - Meng, Electrical And Electronics Engineering

Bachelor Of Science - Bs, Electrical And Electronics Engineering