Conducted failure analysis of high-volume semiconductor memory products from one of North America's most advanced 300 mm chip fabs using high-resolution imaging and nanoscale chemical analysis instrumentation. Interacted with internal customers to identify appropriate analytical methods for pinpointing root cause of failures affecting device yield. Collaborated with other analytical team members and instrumentation vendors to establish most effective techniques for fixing problems and improving yield. Created improved analytical procedures to address novel failure modes.• Played key role in maintaining NAND flash yield of over 90%, interacting daily with manufacturing engineers to increase yield of DRAM and NAND flash devices by identifying origin of defects and particles in failed devices.• Evaluated super-resolution image reconstruction for 50+% resolution improvement and electron tomography (3D imaging) for electron device failure analysis; illustrated limits of resolution in electron microscope imaging.• Reduced analytical team member meeting times by 50% and created orderly, smooth-running operation by establishing routine for setting daily priorities and goals.

Held full responsibility for all day-to-day lab operations, supervising and evaluating team of 8. Characterized advanced semiconductor devices and materials using high-resolution imaging instrumentation; anticipated analytical needs for next- generation devices. Communicated with internal and external customers (engineers, managers, and scientists) to identify and resolve problems using state-of-the-art analytical instrumentation. Upgraded instrumentation hardware and software.• Established procedures for measuring nanoscale strain fields in strained Si:SiGe devices in a joint effort with SEMATECH personnel and other team members. Evaluated several techniques for effectiveness.• Collaborated in successful development of electron holography of electrostatic fields in MOSFET devices with faculty and staff of Arizona State University. Optimized sample preparation of devices, established imaging conditions and data interpretation, and correlated results with known processing parameters of original devices.• Generated higher rate of better samples and improved preparation techniques by implementing quantitative measures of semiconductor sample quality, with feedback provided to sample preparation personnel; applied the resulting techniques to meet challenges of high-resolution imaging of new materials.• Implemented diffraction and crystallography software resources for analytical lab, enabling rapid identification of novel materials; assisted in QS-9000 documentation to ensure high-quality analytical results for products.• Established technical requirements of optimal environment for sensitive analytical equipment.

Provided advanced imaging and analytical capabilities for cutting-edge semiconductor devices within newly-established, state-of-the-art physical analysis laboratory. Led team of 4 technicians and engineer. Projected future analytical needs for nanoscale electronic devices, including atomic characterization and correlation with device processing/performance.• Analyzed and presented data critical for high-profile projects involving some of the world's most advanced semiconductor devices in world-renowned Advanced Products Research & Development Laboratory (APRDL).• Reduced preparation time by over 50% and increased sample yield to over 95% by introducing new sample preparation equipment and procedures in collaboration with Texas Instruments colleagues.• Decreased data distribution times by over 80% and empowered internal customers to make customized requirements on high-resolution images and spectroscopic data in a joint effort with IT and internal customers.• Selected along with 100 other technical staff members among 1,000s to work and live in France as part of a joint venture with Philips Electronics and STMicroelectronics (2003-2005).

Established new facility at Cornell for advanced electronic packaging; served as a reviewer for IEEE Transactions on Components, Packaging, and Manufacturing Technology; established metal deposition, laser machining, photolithography, assembly, and laminography for C4 flip-chip packages.

Characterized adsorbates and films using atomic-resolution electron microscopy, image simulation techniques, and surface science tools. Conducted MBE growth of multiple-layer thin film structures, including metal/oxide, silicide/silicon, and oxide/silicon epitaxial systems.

Designed, fabricated, and tested low-temperature infrared sensor arrays and silicon-based processing arrays for use on surveillance satellites. Held Secret Security Clearance.