Srinivasulu Pola Email & Phone Number

Currently leading the AMS IP development and delivery at Arasan Chip Systems, I bring over a decade of experience in designing and managing silicon-proven Analog Mixed Signal (AMS) IPs for cutting-edge technologies. My expertise spans the complete digital design flow, from RTL to Silicon Validation, combined with a deep understanding of Analog-Digital Partitioning and Testchip Development.- Leading AMS IP development for Super Tier 1 companies, ensuring seamless delivery of high-quality, silicon-proven solutions.- Proven expertise across the semiconductor spectrum, with hands-on experience in advanced technologies ranging from 5nm to 180nm nodes across all major semiconductor foundries.- Comprehensive experience across the entire digital design flow, including RTL, synthesis, timing constraint development, APR, STA, DFT architecture, ATPG, interface timing models, LEC, post-layout digital & AMS simulation- Extensive experience in developing and validating design flows for EDA tools, optimizing processes to enhance design efficiency and accuracy- Experience in Analog-Digital Partitioning, Testchip Development, and Silicon Validation, ensuring reliable and high-performance designs- Have experience in MIPI MPHY, CDPHY, I3C, SW; eMMC51, ONFI, UHS2; USB, xSPI & Analog IP- Adept at project execution and customer support, delivering tailored solutions to meet stringent design & customer requirements

Listed skills include Verilog, Vlsi, Modelsim, Simulations, and 21 others.