Dedicated DFT engineer with a passion lies in developing robust DFT methodologies to streamline the testing process for intricate semiconductor designs. With expertise in scan insertion, ATPG (Automatic Test Pattern Generation), Diagnosis and Simulations, I ensure the efficient detection and diagnosis of faults, contributing to enhanced product reliability and time-to-market efficiency. I excel in leveraging advanced tools and techniques to optimize test coverage and minimize test costs, driving excellence in semiconductor testing.