Pragdev Panda Email & Phone Number

Bengaluru, Karnataka, India

Bangalore

Bangalore

(Moved to Broadcom as part of acquisition of Wireless Modem group of Renesas Mobile by Broadcom)My responsibilities here includes UPF development for complex 28nm Modem IP as defined by the low power strategy. Ensuring the quality of this UPF which is used for PA Verification and Implementation Teams by necessary UPF verification/checks & review with concerned Design Teams.I am also responsible for UPF based Synthesis, defining test clocking strategy , interfacing with SoC Team for implementing all test specific requirements & ensuring DFT readiness of the design. I also contribute to Constraints Development and Static Timing Analysis tasks.

Bangalore

Responsible for overall DFT Strategy, DFT Clocking Design, DFT Constraints, MBIST Insertion, SCAN/LBIST Insertion. Also responsible for test constraints development, STA and review of timing reports.Strategy to reduce test cost & meet low power requirements on 28nm wireless chip & multiple Modem IP versions. RTL Power Estimation using PowerTheater and PT-PX Netlist Level Power Estimation Runs for various Functional Scenarios.

As Senior DFT Engineer handled DFT specific Licensee requirements, SCAN Insertion, & DFT Clocking design. Also worked on TestMode constraints development,STA timing closure.,Spyglass Lint, MoreLint DFTChecks, Spyglass & Conformal CDC Runs. RTL Power Analysis and Power Minimization Techniques with PowerTheater and PT-PX for Netlist Level Power Estimation.

DFT implementation on multi-million gate designs BSCAN/MBIST/SCAN and custom IP testing ( Serdes,PLL,Codec etc )STA Constraints development for TestModes and PrimeTime Timing AnalysisFormality Equivalence Checks ( RTL-RTL & RTL-Gate )Taped out 4 chips while at Open-Silicon