Nagendra Prasad Addagarla Email & Phone Number

Santa Clara, California, Us

Excited to be back and to re-ignite an old flame🔥- CPUs

Menlo Park, Ca, Us

Santa Clara, California, Us

Validation of Deep Learning HW

Santa Clara, California, Us

Created a method of mixing methodologies by keeping them separate.Designed Layered sequences for a P2P protocol routerLead a team of 4 to 8 peopleEnd to end validation of touch controller IP and customer delivery.Resource management, project planning and execution

San Diego, Ca, Us

Worked with the Qualcomm CDMA Technologies (QCT) business unit in the Graphics Design Verification Team. During my stint here I was involved in the verificaiton of the top level grpahics core and the Vertex Parameter Cache sub-block.My work in the top level verification of Graphics core involvedAdding scalability to block level debug monitors for different SP (Shader Processor) configurationsDeveloped injectors to create back pressure scenarios on internal interfaces of the core to test for robustness of the designMy work in the Verification of GPU sub-block VPC involved:Owning an existing Vera TestbenchEnhancing the Vera TB to support the next generation graphics core featuresDesign and review of Functional coverage modelsDeveloping a System Verilog TB using OVM methodology from scratch. Salient features of the TB includes 1) Dual context support 2) Random and Vector stimulus support 3) Out of order checkers 4) Idle interface timeout - better than UVM heart beatConverted the existing OVM TB to UVM in the next generationResponsible for project schedule, test planning, random TB architecture, and Delivery while managing a team of two engineers.

San Jose, Ca, Us

I was part of the Post-Si Validation team that was responsible for the bring up of a SRIO switch ASIC. I was responsible for RTL design of an SRIO RX TX design implemented in an FPGA. The FPGA generated traffic to the ASIC and was controlled by a powerPC. I wrote tcl test cases that ran on the powerPC to test the features of the SRIO ASIC. I was introduced to VERA test benches and TCL scripting at this job.

Us

ASIC Design and Verification and DFT. RTL Design of an ABH IPClock domain crossing micro architecture for HDMI TX and HDMI RXRTL Design of Color Space conversion and Alpha Blending IPsDFT scan synthesisFormal Equivalence checking of an ARM co-processor netlist vs RTL

Functional verification of CAN controller using VHDL and methodology based VHDL testbench.Controller Area NetworkVHDLVerification MethodologyTest planning

M.Tech, Vlsi Design

Certificate Course, Time Management Fundamentals

B.Tech, Electronics And Communication Engineering

X, Maths, Physics, Chemistry, Biology, Social Sciences, English, Hindi And Telugu Languages