Senior Member Of Technical Staff
Current* Work on design verification of AMD's next generation Zen cores.
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Pushpa Prabhuswamy is listed as Senior Member Of Technical Staff at AMD, based in San Francisco Bay Area, United States, United States. AeroLeads shows a work email signal at amd.com and a matched LinkedIn profile for Pushpa Prabhuswamy.
Pushpa Prabhuswamy previously worked as Member Of Technical Staff at Amd and Senior Design Engineer at Amd. Pushpa Prabhuswamy holds Master'S, Computer Engineering from North Carolina State University.
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• 12 years of professional experience in ASIC design and verification.* 10+ experience in verification of next generation CPU cores.* Experience in testbench and checker development.* Experienced in debug and triage of issues. • RTL design background using Verilog and VHDL.• Familiarity with industry standard methodologies – RVM,OVM,VMM.• Proficient in programming and scripting – assembly, C, C++ (Object Oriented), Perl, system verilog.
Listed skills include Systemverilog, Verilog, Perl, Systemc, and 20 others.
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Santa Clara, California, US
* Work on design verification of AMD's next generation Zen cores.
Santa Clara, California, US
* Working on verification of AMD's next generation Zen cores
Santa Clara, California, US
* Working on verification of AMD's next generation cores* Involved in Test bench and checker development. * Development of random pattern generator for core architectural feature verification.
Santa Clara, California, US
Involved in development and maintenance of verification infrastructure for verification of Bulldozer Cores.
US
*Development of block level verification environment using systemverilog.*Development of Test and Coverage plans for verification of SD Host Controller.*Development of SystemVerilog based testbench for CRC Generator and Checker.*Use of SystemVerilog DPI to interface with the SystemC and C models.*Migration of Verilog testbench to a basic SystemVerilog.
CAN Protocol Analyzer: Design of hand-held CAN (Control Area Network) Bus Analyzer based on Windows CE platform for ARM-9 core. The device allows the user to monitor and control the data on a CAN Bus and is mainly used for automotive applications. *Design and development of GPIO, SPI device drivers to interact with the CAN controller.*Development of.
San Jose, CA, US
Involved in pre-silicon block level verification using Open Vera and Reference Verification Methodology(RVM) to construct a constrained-random, transaction-level, self-checking, coverage-driven test environment.
San Jose, CA, US
Worked for the ASIC and Hardware Tools team. Developed and implemented Software applications, shell scripts, perl programs to monitor large network storage and update status on the web and to alert administrators.
Designed and Implemented VHDL and FPGA based Sensitivity Time Control, Synchronization unit for Radar receiver module and Interface unit for RADAR trans receiver. The Sensitivity Time Control Unit was later included as an IP in the RADAR block set library(Xilinx). Published paper available at.
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Pushpa Prabhuswamy works for AMD.
Pushpa Prabhuswamy is listed as Senior Member Of Technical Staff at AMD.
AeroLeads has found 1 work email signal at @amd.com for Pushpa Prabhuswamy at AMD.
Pushpa Prabhuswamy is based in San Francisco Bay Area, United States, United States while working with AMD.
Pushpa Prabhuswamy has worked for Amd, Keyu Tech, Indus-Usa Inc, Cisco Systems, and Electronics And Radar Development Establishment.
Pushpa Prabhuswamy's colleagues at AMD include Yu-Hsuan Liu, Sahith S R, Evoxr Aal, Renee Doucet, and Baesung Kim.
You can use AeroLeads to view verified contact signals for Pushpa Prabhuswamy at AMD, including work email, phone, and LinkedIn data when available.
Pushpa Prabhuswamy holds Master'S, Computer Engineering from North Carolina State University.
Pushpa Prabhuswamy is listed with skills including Systemverilog, Verilog, Perl, Systemc, Asic, Vhdl, Embedded Systems, and C.
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