Raghavan G Email & Phone Number

Experienced in design, functional verification (using VHDL, SV with OVM) and System validation of FPGA based SoCs.> Involved in defining architecture and design of FPGA based SoC> Handled functional verification for multiple complex FPGA designs involving high-speed serial interfaces like Aurora, PCIe and memories such as DDR2, DDR3 and MoSys.> Experienced in Verification plan creation and defining verification environment for multiple FPGA based SoC designs.> Hands on experience in development of self-checking, automated test benches using VHDL, SV and following methodologies such as OVM. > Development, execution, and maintenance of test cases and Code coverage analysis.> Lead and mentor teams and guide the team for effective and timely implementation of the design features not compromising on functional completeness, ease of debug, visualizing the use-case scenarios and end-user's ease of usability. Languages used : VHDL, SystemVerilog, C, VerilogScripting with : TCL, PERL, Python, Shell Have used -- Modelsim and Questasim -- FPGA implementation tools Xilinx ISE and Vivado, chipscope, Libero IDE-- SDK Xilinx SDK and Libero Eclipse for developing bare metal SW application.-- Qt Designer for creating front end GUIs for verification and validation.-- PyDev IDE for creating Python based backed for GUIWorking knowledge of serial data transfer protocols such as Aurora, sFPDP, transaction layer of PCIe, SPI and I2C.Worked with memories such as DDR2, DDR3 and MoSys> Committed and accountable team player with good written and oral communication skills.> Have owned projects and interacted with customers at different stages of the project.> Mentored and lead a team of engineers; creating work breakdown structures and delegating tasks.> Involved in recruitment for both on-campus and off-campus activities.

Listed skills include Test Planning, C, Debugging, Perl, and 19 others.

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  Engineering Manager

  Coreel Technologies

  Apr 2023 - Present